SNLA344C March   2022  – October 2023 DP83826E , DP83826I

 

  1.   1
  2.   How and Why to Use the DP83826E for EtherCAT Applications
  3.   Trademarks
  4. 1Introduction
  5. 2EtherCAT® Specification Requirements and Recommendations
  6. 3Different Methods of Setting up the PHY
    1. 3.1 Using Strap Configuration to Set Up DP83826 PHY for EtherCAT® Configuration
      1. 3.1.1 Strapping Options
    2. 3.2 Using Serial Management Interface to Setup DP83826 PHY
      1. 3.2.1 Programming Options
  7. 4References
  8. 5Revision History

Programming Options

DP83826 register setup

When setting up DP83826 to work for EtherCAT®, the following registers are written as follows:

LED 0
Write to PHY register 0x19 value 0x8020 (Auto-MDIX enable and enable LED0 config) 
Write to PHY register 0x18 value 0x0080 (Active High polarity)
LED 1 
Write to PHY register 0x460 value 0x0005 (100Mbit speed)
Write to PHY register 0x469 value 0x0004 (Active High polarity)
Write to PHY register 0x304 value 0x0008 (Set pin 31 function to LED1) Auto negotiate enable configuration 
Write to PHY register 0x04 value 0x01E1 (Advertise which modes PHY support)
Write to PHY register 0x09 value 0x0020 (Enable Robust Auto MDIX)
Write to PHY register 0x00 value 0x3300 (Enable Auto negotiate and restart process) Odd-nibble Detection Disable Configuration
Write to PHY register 0x0A value 0x0001 (Disable Odd-nibble detection)
Fast Link-Drop Enable
Write to PHY register 0x0B value 0x0008 (Enable FLD with correct FLD features RX Error count)

With the previous write functions, the following register settings can now be read out of both PHYs.

Table 3-3 DP83826 Register Dump in Working EtherCAT® Configuration
Register Address MDIO PHY Address 0x01
0x0 0x3100
0x1 0x786D
0x3 0xA111
0x4 0x1E1
0x5 0xCDE1
0x6 0xD
0x7 0x2001
0x8 0x0
0x9 0x24
0xA 0x100
0xB 0x0
0xF 0x0
0x10 0x4615
0x11 0x10B
0x14 0x0
0x15 0x0
0x17 0x49
0x18 0x480
0x19 0x8C21
Extended Registers (1)
0x25 0x41
0x304 0x8
0x460 0x5
0x469 0x4
Extended Register access requires a 4-step process