SNLA389G October   2022  – December 2025 DP83TC812R-Q1 , DP83TC812S-Q1 , DP83TC813R-Q1 , DP83TC813S-Q1 , DP83TC814R-Q1 , DP83TC814S-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Hardware Configuration
    1. 2.1 Schematic
  6. 3Software Configuration
  7. 4Testing PMA
    1. 4.1 PMA Testing Procedure
  8. 5Testing IOP: Link-up and Link-down
    1. 5.1 IOP Testing Procedure
  9. 6Testing SQI
    1. 6.1 SQI Value Interpretation
  10. 7Testing TDR
    1. 7.1 TDR Testing Procedure
  11. 8Testing EMC and EMI
  12. 9Revision History

3 Software Configuration

This section contains the register settings of DP83TC81x used during tests in different OA compliance test houses. These settings are recommended as the minimum requirement. Further parameters are available to be programmed if required by system- or board-level constraints. The default values listed are read upon power up or hard reset of the device.

The PHY supports bootstrap option to configure in Autonomous or Managed mode and it is in Autonomous mode by default. Managed mode strap option is recommended to prevent the link-up process from initiating while the software configuration from Table 3-1 and Table 3-2 is being executed. Once the software configuration is completed, the PHY can be removed from Managed mode by setting bit 0x18B[6] to ‘1’.

Table 3-1 Master Mode Configuration
MMDREGISTERVALUEDESCRIPTION
1fx001Fx8000Hard reset
1fx0523x0001To disable link-up start until configuration is complete
01x0834xC000To configure PHY in Master mode
1fx081Cx0FE2Configuration for Interoperability
1fx0873x0021Configuration for Interoperability
1fx089Ex0010Configuration for Interoperability
1fx0874x6866Configuration for Interoperability
1fx0875x6868Configuration for Interoperability
1fx0812x00EEConfiguration for Interoperability
1fx0816x0300Configuration for Interoperability
1fx0806x293AConfiguration for Interoperability
1fx0807x3348Configuration for Interoperability
1fx0808x3D56Configuration for Interoperability
1fx083Ex045FConfiguration for Interoperability
1fx0834x8000Configuration for Interoperability
1fx0862x0330Configuration for Interoperability
1fx0896x32CBConfiguration for Interoperability
1fx003Ex0009Configuration for Interoperability

1f

x0848

x0030

Configuration for Interoperability
1fx0830x0143Configuration for Interoperability

1f

x080A

x0015

Configuration for Interoperability
1fx0820x03AAConfiguration for Interoperability
1fx0826x1407Configuration for Interoperability
1fx083Dx0047Configuration for Interoperability
1fx086Cx1336Configuration for Interoperability
1fx0856x1000Configuration for Interoperability
1fx0842xBAB8Configuration for Interoperability
1fx08F3x0015Configuration for Interoperability
1fx08ADx0019Configuration for Interoperability
1fx08EDx001DConfiguration for Interoperability
1fx08EFx0021Configuration for Interoperability

1f

x08F0

x0025

Configuration for Interoperability

1f

x08F1

x0029

Configuration for Interoperability

1f

x08F2

x002D

Configuration for Interoperability

1f

x0456

x0021

Reduce the slew rate of MAC interface IO drivers
1fx0452x0303(Optional): Disable CLKOUT and LED outputs to reduce emissions
1fx0453x0003
1fx045Fx000F
1fx085Ax3000Configuration to improve RF immunity performance
1fx085Bx3000
1fx0189x0018Configuration for TC10 Interoperability
1fx018Bx144B
1fx0154

x0220

Configuration for Interoperability
1fx001Fx4000Soft reset
1fx0523x0000Enable link-up start after end of configuration
Table 3-2 Slave Mode Configuration
MMDREGISTERVALUEDESCRIPTION
1fx001Fx8000Hard reset
1fx0523x0001To disable link-up start until configuration is complete
01x0834x8000To configure PHY in Slave mode
1fx0862x0330Configuration for Interoperability
1fx086Ex1868Configuration for Interoperability
1fx0812x00F4Configuration for Interoperability
1fx0816x0300Configuration for Interoperability
1fx0873x0021Configuration for Interoperability
1fx0896x22FFConfiguration for Interoperability
1fx089Ex0000Configuration for Interoperability

1f

x08F3

x0015

Configuration for Interoperability

1f

x08AD

x0019

Configuration for Interoperability

1f

x08ED

x001D

Configuration for Interoperability

1f

x08EF

x0021

Configuration for Interoperability

1f

x08F0

x0025

Configuration for Interoperability

1f

x08F1

x0029

Configuration for Interoperability

1f

x08F2

x002D

Configuration for Interoperability
1fx0456x0021Reduce the slew rate of MAC interface IO drivers
1fx0452x0303(Optional): Disable CLKOUT and LED outputs to reduce emissions
1fx0453x0003
1fx045Fx000F
1fx085Ax3000Configuration to improve RF immunity performance
1fx085Bx3000
1fx0189x0018Configuration for TC10 Interoperability
1fx018Bx144B

1f

x0154

x0220

Configuration for Interoperability
1fx001Fx4000Soft reset
1fx0523x0000Enable link-up start after end of configuration