SPRACI9A October   2018  – July 2021 AM6526 , AM6528 , AM6546 , AM6548

 

  1.   Trademarks
  2. 1Introduction
  3. 2Recommendations Specific to the AM65x/DRA80x
    1. 2.1  EVM versus Data Sheet
    2. 2.2  Power
    3. 2.3  Reset
    4. 2.4  Boot Modes
    5. 2.5  Unused Signals
    6. 2.6  Clocking
    7. 2.7  System Issues
    8. 2.8  Low Power Considerations
    9. 2.9  DDR
    10. 2.10 MMC
    11. 2.11 OSPI and QSPI
    12. 2.12 GPMC NAND
    13. 2.13 I2C
    14. 2.14 CPSW Ethernet
    15. 2.15 ICSSG
    16. 2.16 USB
    17. 2.17 SERDES - USB3
    18. 2.18 SERDES - PCIe
    19. 2.19 JTAG and EMU
  4. 3References
  5. 4Revision History

CPSW Ethernet

  • Have you correctly configured the initial configuration for your PHY? Most PHYs use the signals normally driven by the PHY to capture the initial configuration, using pull-up and pull-down resistors. The TI PHY used on the AM65x/DRA80x EVM uses both to generate a mid-level voltage, allowing four separate configurations per pin. By default in the AM65x/DRA80x, both the receiver buffers and the internal pulling resistors are disabled at reset. The PHYs should be removed from reset, allowing the initial configuration to be captured before enabling either the receiver buffers or the internal pulling resistors.
  • Have you terminated your RGMII signals correctly? For the RGMII interfaces, 22-Ω series termination resistors must be placed on all 12 interface signals as close to the transmitter as possible.