Additional details of each parameter of this section can be found in the list below:

1. Board Project Name:
   1. Description: This parameter is not used in version 0.10.0 or earlier of the Jacinto 7 DDRSS Register Configuration Tool.
   2. Valid Values: NA
   3. Recommended Value: NA
2. TI System-on-Chip (SoC) Part Number:
   1. Description: Defines the TI processor part number used in the system.
   2. Valid Values: Defined by a drop-down menu list, matching the supported TI processors by the tool.
   3. Recommended Value: This parameter must be selected to match the TI processor part number being used in the system. The output of the tool could vary depending on the selected SoC, so it is imperative that the correct part number is used!
3. DDR Controllers Utilized in System:
   1. Description: Defines which DDRSS instances of the TI SoC are connected to external memory and should be configured by software.
   2. Valid Values: Defined by a drop-down menu list, matching the supported combination of DDR sub-systems that can be enabled for the selected TI SoC.
   3. Recommended Value: N/A
      Note: The drop-down list for this parameter is dependent on the user input of the 'TI SoC Part Number.
4. DDR Memory Type:
   1. Description: Defines the type of DDR memory used in the system.
   2. Valid Values: Defined by a drop-down menu list, matching the supported DDR memory types by the tool.
   3. Recommended Value: Only one option, "LPDDR4", is supported by the tool.
5. DDR Memory Boot Frequency (Frequency Set 0):
   1. Description: Defines the DDR memory clock frequency during the DRAM initialization, or tCKb as defined in the specific DDR component data sheet.
   2. Valid Values: For supported tCKb frequencies, see the specific DDR component data sheet.
   3. Recommended Value: It is recommended to match the TI default value.
   Note: The usage of this parameter has different impact depending on the versions of SDK and Jacinto 7 DDRSS Register Configuration Tool being used. Prior to SDK8.0 and Jacinto 7 DDRSS Register Configuration Tool version 0.6.0, this parameter impacted the *_F0 timing parameters but did NOT control the actual LPDDR4 boot frequency. Rather, the LPDDR4 boot frequency is 2x the PLL12 bypass clock, or 2x the oscillator frequency, in SDKs released prior to SDK8.0. Starting with SDK8.0 and Jacinto 7 DDRSS Register Configuration Tool version 0.6.0, this parameter impacts both the *_F0 timing parameters and the LPDDR4 boot frequency.
6. DDR Memory Frequency (Frequency Set 1):
   1. Description: Defines the target DDR memory clock frequency during normal operation when the LPDDR4 is configured for frequency set point 0.
   2. Valid Values: Not configurable. As the tool does not support different frequency set points, this value must match input parameter DDR Memory Frequency (Frequency Set 2), and automatically updates in the tool to reflect this requirement.
   3. Recommended Value: NA
7. DDR Memory Frequency (Frequency Set 2):
   1. Description: Defines the target DDR memory clock frequency during normal operation when the LPDDR4 is configured for frequency set point 1.
   2. Valid Values: For supported frequencies, see the TI device-specific data sheet, as well as the specific DDR component data sheet. Note that this parameter should be set to the clock rate, and not the data rate.
   3. Recommended Value: Value must be within the min/max supported limits of both the TI processor DDRSS and DDR.
8. DDR Data Bus Width:
   1. Description: Defines the bus width utilized by the DDR interface.
   2. Valid Values: Defined by a drop-down menu list, matching the supported bus widths by the tool.
   3. Recommended Value: Value should be set to match the number of physical data (DQ) IO pins which are connected between the processor's DDRSS and the LPDDR4 memory on the printed circuit board (PCB).
9. DDR Density:
   1. Description: Defines the density of a single channel from a single rank of the LPDDR4 memory. As an example, if the LPDDR4 memory has total density of 32Gb across 2 channels and 2 ranks, then this parameter should be set to 8Gb. Or if the LPDDR4 memory has total density of 8Gb across 2 channels and 1 rank, then this parameter should be set to 4Gb.
   2. Valid Values: Defined by a drop-down menu list, matching the supported densities by the tool.
   3. Recommended Value: Value should be set to match the density, as described by this parameter's description, of the LPDDR4 used in the system.
10. Chip Selects / Ranks:
    1. Description: Defines the number of ranks, or chip selects, utilized for the DDR interface. Although the LPDDR4 interface has a unique chip select for each channel, usage of CS0_A and CS0_B should be considered 1 rank. Usage of CS0_A and CS1_A should be considered 2 ranks. In other words, this parameter defines the number of chip selects per channel.
    2. Valid Values: Defined by a drop-down menu list, matching the supported ranks by the tool.
    3. Recommended Value: Value should be set to match the number of ranks, as described by this parameter's description, utilized by the DDR interface.
11. Enable DRAM Temperature Polling:
    1. Description: This parameter enables or disables LPDDR4 temperature polling during normal operation. When enabled, the controller will periodically send a Mode Register Read request to the LPDDR4 to read MR4. The purpose of enabling DRAM temperature polling would be to dynamically change the refresh rate depending on the temperature of the LPDDR4.
    2. Valid Values: Defined by a drop-down menu list.
    3. Recommended Value: Usage of this feature will be system dependent, and could be impacted by the temperatures the LPDDR4 may be subject to in the end application, as well as by throughput requirements of the system.
    Note: Enabling this parameter ONLY allows the controller to periodically read MR4 of the LPDDR4. It does NOT change the refresh rate. A software interrupt service routine is required to service the changes in temperature.

    If the refresh rate is not changed dynamically, you should ensure that the fastest refresh rate required by the LPDDR4 is programmed in the corresponding timing parameters in the "DRAMTiming" worksheet.

    Temperature de-rating must be accounted for in the "DRAMTiming" worksheet, regardless of the configuration of this parameter.

12. System Temperature Gradient:
    1. Description: Defines the maximum temperature gradient the system, specifically the DDR, will be subject to in the target end application. In other words, this parameter defines how quickly the temperature of the DDR will change.
    2. Valid Values: Any decimal value greater than zero.
    3. Recommended Value: NA, this parameter is system dependent and must be defined by the end user.
    Note: This parameter is not used when DRAM temperature polling is disabled.
13. Multi DDRSS Interleave Hybrid Config
    1. Description: Determines how the DDR subsystems are interleaved when multiple DDR subsystems are in use.
    2. Valid Values: Defined by a drop-down menu list, matching the supported configurations for the selected TI SOC and number of DDR subsystems in use.
14. Multi DDRSS Interleave Memory Size
    1. Description: Determines the size of the interleaved memory region.
    2. Valid Values: Defined by a drop-down menu list, matching the supported configurations based on the number of DDR subsystems in use and the corresponding LP4 memories connected.
15. Multi DDRSS Interleave Granularity
    1. Description: Determines the granularity at which the DDR subsystems are interleaved within the interleaved memory region.
    2. Valid Values: Defined by a drop-down menu list, matching the supported configurations based on the number of DDR subsystems in use and the interleaved memory region size.