SPRAD59 October   2023 TMS320F280039

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Key Differences Between DCAN and MCAN
  6. 3 Module Initialization
    1. 3.1 DCAN Initialization
    2. 3.2 MCAN Initialization
    3. 3.3 Initialization sequence
    4. 3.4 Code Snippets for Module Initialization
  7. 4 Bit Timing Configuration
  8. 5 Message RAM Configuration
  9. 6 Interrupt handling
    1. 6.1 MCAN Interrupt Sources
    2. 6.2 DCAN Interrupt Handling
    3. 6.3 MCAN Interrupt Handling
  10. 7 Transmitting data
    1. 7.1 Basic Transmission Process
      1. 7.1.1 Transmission with DCAN
      2. 7.1.2 Transmission with MCAN
    2. 7.2 MCAN Vs DCAN Transmit Procedural Differences
    3. 7.3 MCAN Transmit Concepts
      1. 7.3.1 Tx Event FIFO
  11. 8 Receiving Data
    1. 8.1 Introduction to Reception
    2. 8.2 Basic Reception Process
      1. 8.2.1 DCAN Reception
      2. 8.2.2 MCAN Reception
    3. 8.3 Filter Elements
      1. 8.3.1 Filter Element Structure
    4. 8.4 Rx Buffer
      1. 8.4.1 Receiving in Rx Buffer
    5. 8.5 Rx FIFO
      1. 8.5.1 Receiving in Rx FIFO
    6. 8.6 Receiving High Priority Messages
  12. 9 Avoiding network errors
  13. 10References

7.3 MCAN Transmit Concepts

This section outlines the additional features in MCAN.

  • Each Tx Message can be configured to transmit in Classic CAN or CAN-FD mode
  • Transmit Pause
  • Transmit Cancellation
  • Tx FIFO / Tx Queue

Within the Message RAM, the Tx Buffer space can have the following possible configurations:

  1. Only Tx Buffers
  2. Tx Buffers + Tx FIFO
  3. Tx Buffers + Tx Queue
How to configure each of these sections has been displayed in Table 7-2 below:

Table 7-2 Message RAM Configuration for Various Tx Buffer Options
Tx BuffersTx Buffers + Tx FIFOTx Buffers + Tx Queue

txBufNum = BUFF_SIZE

(MCAN_TXBC.NDTB)

txFIFOSize = 0

(MCAN_TXBC.TFQS)

txBufNum = BUFF_SIZE

(MCAN_TXBC.NDTB)

txFIFOSize = FIFO_SIZE

(MCAN_TXBC.TFQS)

txBufMode = 0

(MCAN_TXBC.TFQM)

txBufNum = BUFF_SIZE

(MCAN_TXBC.NDTB)

txFIFOSize = QUE_SIZE

(MCAN_TXBC.TFQS)

txBufMode = 1

(MCAN_TXBC.TFQM)

The differences in functionality and potential use cases for each of the sections have been specified in Table 7-3 below:

Table 7-3 Tx Buffers Vs Tx FIFO Vs Tx Queue Feature Comparison
FeatureTx BuffersTx FIFOTx Queue
Information directly available to host (CPU)Buffer Element number is known.Only Put and Get indices can be read from a register (MCAN_TXFQS)Only Put and Get indices can be read from a register (MCAN_TXFQS)
Element transmitted firstElement with lowest message IDOldest ElementElement with lowest message ID
Put Index / Get IndexNot applicable

Put index points to where the most recent frame is stored. Incremented with Add Transmit Request.Get index points to the oldest element, which is be transmitted next.

Put index points to the lowest, free buffer element (within the queue), where the most recent frame is stored. Updated with Add Transmit Request.

Get index is always Zero
Transmission of multiple messages with same IDElement with lowest buffer number is transmittedOldest Element is transmittedElement with lowest buffer number is transmitted
Full ConditionNot applicableIn case FIFO is full, no message can be written unless a requested transmission is completedIn case queue is full, no message can be written unless a requested transmission is completed
Tx CancellationPossibleNot PossibleNot Possible
Use CasesAdvantage is that the application knows which message ID is stored in which buffer element and hence, can be edited before sendingApplications where frames have to be transmitted in a specific order, not following increasing order of message IDsAdvantage is that buffer number is automatically handled by the Put index. Application need not track which buffer is empty based on the message ID priority
GUID-20231010-SS0I-VJ3R-ZWHF-CC1RXKRG0ZDP-low.pngFigure 7-2 Transmission with MCAN