SPRAD66A February   2023  – December 2023 AM62A3 , AM62A3-Q1 , AM62A7 , AM62A7-Q1 , AM62P , AM62P-Q1

 

  1.   1
  2.    AM62Ax/AM62Px LPDDR4 Board Design and Layout Guidelines
  3.   Trademarks
  4. 1Overview
    1. 1.1 Board Designs Supported
    2. 1.2 General Board Layout Guidelines
    3. 1.3 PCB Stack-Up
    4. 1.4 Bypass Capacitors
      1. 1.4.1 Bulk Bypass Capacitors
      2. 1.4.2 High-Speed Bypass Capacitors
    5. 1.5 Velocity Compensation
  5. 2LPDDR4 Board Design and Layout Guidance
    1. 2.1  LPDDR4 Introduction
    2. 2.2  LPDDR4 Device Implementations Supported
    3. 2.3  LPDDR4 Interface Schematics
    4. 2.4  Compatible JEDEC LPDDR4 Devices
    5. 2.5  Placement
    6. 2.6  LPDDR4 Keepout Region
    7. 2.7  Net Classes
    8. 2.8  LPDDR4 Signal Termination
    9. 2.9  LPDDR4 VREF Routing
    10. 2.10 LPDDR4 VTT
    11. 2.11 CK and ADDR_CTRL Topologies
    12. 2.12 Data Group Topologies
    13. 2.13 CK0 and ADDR_CTRL Routing Specification
    14. 2.14 Data Group Routing Specification
    15. 2.15 Channel, Byte, and Bit Swapping
    16. 2.16 Data Bus Inversion
  6. 3LPDDR4 Board Design Simulations
    1. 3.1 Board Model Extraction
    2. 3.2 Board-Model Validation
    3. 3.3 S-Parameter Inspection
    4. 3.4 Time Domain Reflectometry (TDR) Analysis
    5. 3.5 System Level Simulation
      1. 3.5.1 Simulation Setup
      2. 3.5.2 Simulation Parameters
      3. 3.5.3 Simulation Targets
        1. 3.5.3.1 Eye Quality
        2. 3.5.3.2 Delay Report
        3. 3.5.3.3 Mask Report
    6. 3.6 Design Example
      1. 3.6.1 Stack-Up
      2. 3.6.2 Routing
      3. 3.6.3 Model Verification
      4. 3.6.4 Simulation Results
  7. 4Appendix: SOC Package Delays
  8. 5References
  9. 6Revision History

2.5 Placement

Figure 2-4 shows an example placement for the AM62Ax/AM62Px processor and the LPDDR4 memory device. The recommended spacing parameters for the AM62Ax/AM62Px device and the LPDDR4 device are defined in Table 2-3. The placement does not restrict the side of the PCB on which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace lengths and allow for proper routing space.

GUID-20221111-SS0I-N3CB-S2R3-ZXZD5P51BXDX-low.svg Figure 2-4 AM62Ax/AM62Px and LPDDR4 Example Placement (Top View)
Table 2-3 LPDDR4 Placement Recommendations
Number Parameter MIN MAX UNIT
1 x1 1200 Mils
2 y1 250 Mils