2 Procedure to use the Tool

Identify the DCC instance that can be used to monitor the clock source that you require, from the tool or the device technical reference manual.

1. In the (1) Input Section:
   1. Input the frequency of clock being provided as external reference clock in the field EXT_REFCLK frequency input in the DCC instance section being used.
   2. Input the clock source to be used as reference clock for comparison, DCCCLKSSRC0 (Reference Clock) using the provided drop-down menu. The options present are EXT_REFCLK, RCCLK10M (10 MHz), RCCLK32K (32 KHz) and XTALCLK (25 MHz).
   3. Input the clock source to be used for verification, DCCCLKSSRC1 (Clock to be verified) using the provided drop-down menu. The options present are EXT_REFCLK, R5SS0_CLK (400 MHz), R5SS1_CLK (400 MHz), RCCLK32K (32 KHz), SYSCLK (200 MHz) and XTALCLK (25 MHz).
   4. Input the clock accuracy % required for your application. If no input is provided, the tool uses the default value of 0.2 or the minimum possible accuracy (whichever is higher).
   5. Based on the clock sources provided as input, Async Error, DCC Error, Minimum accuracy possible, Window, Frequency Error Allowed, Total error (formula defined in previous section) are computed by the tool.
      Note: Minimum accuracy possible cannot be greater than 48 (beyond which the counter seed value goes to zero), in such clock source combinations, an “ERROR” is displayed.
2. From the (2) Register Configuration Section:
   1. Program the DCCCNTSEED0 (@0x00000008) with the hexadecimal of the Counter0 seed value computed in previous step.
   2. Program the DCCCNTSEED1 (@0x00000010) with the hexadecimal of the Counter1 seed value computed in previous step.
   3. Program the DCCVALIDSEED0 (@0x0000000C) with the hexadecimal of the Valid0 seed value computed in previous step.
   4. Program the DCCCLKSRC0 (@0x00000028) with the corresponding (A000 + hexadecimal index of the clock source 0 that is chosen).
   5. Program the DCCCLKSRC1 (@0x00000024) with the corresponding (A000 + hexadecimal index of the clock source 1 that is chosen).
   6. After all the above configuration is done, set the DCCGCTRL (@0x00000000) with 0x0000AAAA to set the comparison in SINGLE_SHOT mode, enable done signal, enable error signal and start the comparison.
      Note: For continuous mode, configure bits 11:8 with 0101.

   7. At the end of the DCC completion phase, the DCC generates a DCC_done interrupt to R5F if the clock is within the configured tolerance. The Done bit (bit 1) in the register DCCSTAT(@0x00000014) will be set to 1 to indicate the completion.

      If the DCC detects an error in the frequency measurement, then it generates DCCx_error to ESM (Error signaling module) instead of the DCC_done interrupt to R5F. The Error status (bit 0) in the register DCCSTAT(@0x00000014) will be set to 1 to indicate Error condition. In this case, the ESM can be configured to generate an interrupt to R5F or Device Error pin for further action. See the device technical reference manual for details on configuring and setting up the interrupts.

      If interrupt mode is not used, after configuring the SINGLE_SHOT mode, R5F can be configured to continuously poll Error status (bit 0) and Done bit (bit 1) in the register DCCSTAT(@0x00000014).

3. In case an error is obtained, the counter0, counter1 and valid0 values can be read out (from the address offsets 0x00000018, 0x00000020 and 0x0000001C, respectively) in-order to determine the type of error (clock0/clock1 is absent or clock1 expired before the counter0 reaches 0 or clock1 expired after both counter0 and valid0 reach 0).

The above example is for DCC0. Follow similar procedure to use any of the other DCC instances DCC1, DCC2 and DCC3.