Though the software workaround is simple, but would require extra code and CPU bandwidth to monitor the PWM time base counter, and needs to spend CPU cycles waiting for the available timing for PWM register update. For a typical register update including TBPRD, CMPx and TBPHS register, it requires ~50 CPU cycles, which equals ~0.5μs for a 100Mhz CPU, which takes 5% for 100kHz interrupt.

Figure 3-3 CLB Workaround Block Diagram

Another options is to implement the PWM updating nesting logic in the configurable logic block (CLB). The solution introduce original control interrupt signal and a PWM updating forbidden signal in to CLB, and generate another CLB interrupt to trigger the real control loop interrupt. With the logic inside CLB, all the original control interrupts happen during the PWM updating forbidden signal will be nested, so no control loop interrupt will be triggered, and all the risk of PWM disorder will the eliminated.

Figure 3-4 CLB Tile Configuration

Figure 3-5 CLB Workaround Testing Result