A simple workaround can be achieved with the following method:

while(EPwm1Regs.TBCTR>(EPwm1Regs.TBPRD – PwmUpdateTime))
{
} // Wait in while if there is no enough time for PWM register update.
PWMRegsUpdate(); //Function to update PWM shadow registers. Make sure to put all register updating code here before seting global load one-shot bit
EPwm1Regs.GLDCTL2.all = 1;

Where PwmUpdateTime is a constant that represents the time cycles reserved for PWM shadow register writing.

By doing this, a time period before the PWM cycle end is reserved. If the PWM updating happens during the reserved period, the CPU will run in a while loop and not to write PWM shadow registers until the reserved time period has passed. In this way, even GLDCTL2[OSHTLD] is set by a previous ISR in the same switching cycle, no mismatched PWM register update will happen.