SPRUJ51A June   2023  – November 2025

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Device Information
    4. 1.4 EVM Revisions and Assembly Variants
    5. 1.5 Specification
  6. 2Hardware
    1. 2.1  Additional Images
    2. 2.2  Key Features
      1. 2.2.1 Processor
      2. 2.2.2 Memory
      3. 2.2.3 JTAG Emulator
      4. 2.2.4 Supported Interfaces and Peripherals
      5. 2.2.5 Expansion Connectors Headers to Support Application Specific Add On Boards
    3. 2.3  Power
      1. 2.3.1 Power Requirements
      2. 2.3.2 Power Input
      3. 2.3.3 Power Supply
      4. 2.3.4 Power ON OFF Procedures
        1. 2.3.4.1 Power-On Procedure
        2. 2.3.4.2 Power-Off Procedure
        3. 2.3.4.3 Power Test Points
      5. 2.3.5 Power Sequencing
      6. 2.3.6 AM62x 17x17 SoC Power
      7. 2.3.7 Current Monitoring
    4. 2.4  AM62x-Low Power SK EVM Interface Mapping
    5. 2.5  Clocking
    6. 2.6  Reset
    7. 2.7  OLDI Display Interface
    8. 2.8  CSI Interface
    9. 2.9  Audio Codec Interface
    10. 2.10 HDMI Display Interface
    11. 2.11 JTAG Interface
    12. 2.12 Test Automation Header
    13. 2.13 UART Interface
    14. 2.14 USB Interface
      1. 2.14.1 USB2.0 Type A Interface
      2. 2.14.2 USB2.0 Type C Interface
    15. 2.15 Memory Interfaces
      1. 2.15.1 LPDDR4 Interface
      2. 2.15.2 OSPI
      3. 2.15.3 MMC Interfaces
        1. 2.15.3.1 MMC0 - eMMC Interface
        2. 2.15.3.2 MMC1 - Micro SD Interface
        3. 2.15.3.3 MMC2 - M2 Key E Interface
      4. 2.15.4 EEPROM
    16. 2.16 Ethernet Interface
      1. 2.16.1 CPSW Ethernet PHY1 Default Configuration
      2. 2.16.2 CPSW Ethernet PHY2 Default Configuration
    17. 2.17 GPIO Port Expander
    18. 2.18 GPIO Mapping
    19. 2.19 AM62x-Low Power SK EVM User Setup and Configuration
      1. 2.19.1 EVM DIP Switches
      2. 2.19.2 Boot Modes
      3. 2.19.3 User Test LEDs
    20. 2.20 Expansion Headers
      1. 2.20.1 User Expansion Connector
      2. 2.20.2 MCU Connector
      3. 2.20.3 PRU Connector
    21. 2.21 Push Buttons
    22. 2.22 I2C Address Mapping
  7. 3Hardware Design Files
  8. 4Compliance Information
    1. 4.1 EMC, EMI and ESD Compliance
  9. 5Additional Information
    1. 5.1 Known Issues and Modifications
    2.     Trademarks
    3.     72
  10. 6Revision History

2.3.4.3 Power Test Points

Test points for each power output on the board are mentioned in Table 2-3.

Table 2-3 Power Test Points
Sl # Power Supply Test Point Voltage
1 VBUS_TYPEC1 R165.1 5V-15V
2 VBUS_TYPEC2 R214.1 5V-15V
3 VMAIN TP73 5V-15V
4 VCC_5V0 TP76 5V
5 VCC_3V3_MAIN TP56 3.3V
6 VCC3V3_TA TP91 3.3V
7 VCC_3V3_SYS TP54 3.3V
8 VCC_CORE TP39 0.75V
9 VCC1V8_SYS TP44 1.8V
10 VCC1V1 TP49 1.1V
11 VDDSHV_SDIO TP41 1.8V/3.3V
12 VCC_0V85 TP51 0.85V
13 VDDA1V8 TP52 1.8V
14 VDD_1V2 TP53 1.2V
15 VDD_2V5 TP40 2.5V
16 VPP_1V8 TP33 1.8V
17 VDD_1V0 TP35 1.0V
18 VCC_CSI_IO C12.1 1.8V/3.3V
19 VCC3V3_EXP C192.1/J3.1 3.3V
20 VCC5V0_EXP C185.1/J3.2 5.0V
21 VCC3V3_PRU C384.1/J11.1 3.3V
22 VDD_MMC1 C39.1/FL8.1 3.3V
23 VBUS_5V0_TYPEA1 C375.1/C110.1 5.0V
24 XDS_USB_VBUS(1) TP90 5.0V
25 VCC3V3_XDS(1) TP81 3.3V
26 FT4232_USB_VBUS(2) J17.1 5.0V
27 VCC_3V3_FT4232(2) LD10.2 3.3V
28 VCC_1V8_FT4232(2) C166.2 1.8V
(1) This voltage is available only when micro B to type A USB cable is connected between J18 and host PC.
(2) This voltage is available only when micro B to type A USB cable is connected between J17 and host PC.