SPRUJ51A June   2023  – November 2025

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Device Information
    4. 1.4 EVM Revisions and Assembly Variants
    5. 1.5 Specification
  6. 2Hardware
    1. 2.1  Additional Images
    2. 2.2  Key Features
      1. 2.2.1 Processor
      2. 2.2.2 Memory
      3. 2.2.3 JTAG Emulator
      4. 2.2.4 Supported Interfaces and Peripherals
      5. 2.2.5 Expansion Connectors Headers to Support Application Specific Add On Boards
    3. 2.3  Power
      1. 2.3.1 Power Requirements
      2. 2.3.2 Power Input
      3. 2.3.3 Power Supply
      4. 2.3.4 Power ON OFF Procedures
        1. 2.3.4.1 Power-On Procedure
        2. 2.3.4.2 Power-Off Procedure
        3. 2.3.4.3 Power Test Points
      5. 2.3.5 Power Sequencing
      6. 2.3.6 AM62x 17x17 SoC Power
      7. 2.3.7 Current Monitoring
    4. 2.4  AM62x-Low Power SK EVM Interface Mapping
    5. 2.5  Clocking
    6. 2.6  Reset
    7. 2.7  OLDI Display Interface
    8. 2.8  CSI Interface
    9. 2.9  Audio Codec Interface
    10. 2.10 HDMI Display Interface
    11. 2.11 JTAG Interface
    12. 2.12 Test Automation Header
    13. 2.13 UART Interface
    14. 2.14 USB Interface
      1. 2.14.1 USB2.0 Type A Interface
      2. 2.14.2 USB2.0 Type C Interface
    15. 2.15 Memory Interfaces
      1. 2.15.1 LPDDR4 Interface
      2. 2.15.2 OSPI
      3. 2.15.3 MMC Interfaces
        1. 2.15.3.1 MMC0 - eMMC Interface
        2. 2.15.3.2 MMC1 - Micro SD Interface
        3. 2.15.3.3 MMC2 - M2 Key E Interface
      4. 2.15.4 EEPROM
    16. 2.16 Ethernet Interface
      1. 2.16.1 CPSW Ethernet PHY1 Default Configuration
      2. 2.16.2 CPSW Ethernet PHY2 Default Configuration
    17. 2.17 GPIO Port Expander
    18. 2.18 GPIO Mapping
    19. 2.19 AM62x-Low Power SK EVM User Setup and Configuration
      1. 2.19.1 EVM DIP Switches
      2. 2.19.2 Boot Modes
      3. 2.19.3 User Test LEDs
    20. 2.20 Expansion Headers
      1. 2.20.1 User Expansion Connector
      2. 2.20.2 MCU Connector
      3. 2.20.3 PRU Connector
    21. 2.21 Push Buttons
    22. 2.22 I2C Address Mapping
  7. 3Hardware Design Files
  8. 4Compliance Information
    1. 4.1 EMC, EMI and ESD Compliance
  9. 5Additional Information
    1. 5.1 Known Issues and Modifications
    2.     Trademarks
    3.     72
  10. 6Revision History

2.19.2 Boot Modes

The boot mode for the AM62x-Low power SK EVM board is defined by two banks of switches SW3 and SW4 or by the I2C buffer connected to the Test automation connector. This allows for AM62x SoC Boot mode control by either the user (DIP Switch Control) or by the Test Automation connector.

All the bits of switch (SW3 & SW4) have week pull down resistor and a strong pull up resistor as shown in below picture. Note that OFF setting provides a low logic level (‘0’) and an ON setting provides a high logic level (‘1’).

Boot Mode Switch Example

The boot mode pins of the SoC have associated alternate functions during normal operation. Hence isolation is provided using Buffer IC’s to cater for alternate pin functionality. The output of the buffer is connected to the bootmode pins on the AM62x Low Power SK EVM. The output is enabled when the bootmode is needed during a reset cycle.

The input to the buffer is connected to the DIP switch circuit and to the output of an I2C buffer set by the test automation circuit. If the test automation circuit is going to control the bootmode, all the switches will manually be set to the OFF position. The bootmode buffer should be powered by an always ON power supply to ensure that the bootmode remains present even if the SoC power is cycled.

Switch SW1 and SW2 bits [15:0] are used to set the SoC Boot mode.

The switch map to the boot mode functions is provided in the tables below.

Figure 2-25 Boot Mode Switch Example
Table 2-17 Boot Mode Pin Mapping
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Reserved Backup Boot Mode Configuration Backup Boot Mode Primary Boot Mode Configuration Primary Boot Mode PLL Configuration

BOOT-MODE[0:2] – Denote system clock frequency for PLL configuration. By default this bits are set for 25MHz.

Table 2-18 PLL Reference Clock Selection
SW3.3 SW3.2 SW3.1 PLL REF CLK (MHz)
OFF OFF OFF RSVD
OFF OFF ON RSVD
OFF ON OFF 24
OFF ON ON 25
ON OFF OFF 26
ON OFF ON RSVD
ON ON OFF RSVD
ON ON ON RSVD

BOOT-MODE [3:6] – This provides primary boot mode configuration to select the requested boot mode after POR, that is, the peripheral/memory to boot from primary boot device selection details.

Table 2-19 Boot Device Selection BOOT-MODE [6:3]
SW3.7 SW3.6 SW3.5 SW3.4 Primary Boot Device Selected
OFF OFF OFF OFF Serial NAND
OFF OFF OFF ON OSPI
OFF OFF ON OFF QSPI
OFF OFF ON ON SPI
OFF ON OFF OFF Ethernet RGMII1
OFF ON OFF ON Ethernet RMII1
OFF ON ON OFF I2C
OFF ON ON ON UART
ON OFF OFF OFF MMC/SD card
ON OFF OFF ON eMMC
ON OFF ON OFF USB0
ON OFF ON ON GPMC NAND
ON ON OFF OFF GPMC NOR
ON ON OFF ON Rsvd
ON ON ON OFF xSPI
ON ON ON ON No boot/Dev Boot

• BOOT-MODE [10:12] – Select the backup boot mode, used when the primary boot mode is not available.

Table 2-20 Backup Boot Mode Selection BOOT-MODE [12:10]
SW4.5 SW4.4 SW4.3 Backup Boot Device Selected
OFF OFF OFF None (No backup mode)
OFF OFF ON USB
OFF ON OFF Reserved
OFF ON ON UART
ON OFF OFF Ethernet
ON OFF ON MMC/SD
ON ON OFF SPI
ON ON ON I2C

BOOT-MODE [9:7] – These pins provide optional settings and are used in conjunction with the primary boot device selected.

Table 2-21 Primary Boot Media Configuration BOOT-MODE[9:7]
SW4.2 SW4.1 SW3.8 Boot Device
Reserved Read Mode 2 Read Mode 1 Serial NAND
Reserved Iclk Csel QSPI
Speed Iclk Csel OSPI
Reserved Mode Csel SPI
Clkout 0 Link stat Ethernet RGMII
Clkout Clk src 0 Ethernet RMII
Bus Reset Reserved Addr I2C
Reserved Reserved Reserved UART
Port Reserved Fs/raw MMC/ SD card
Reserved Reserved Reserved eMMC
Core Volt Mode Lane swap USB0
Reserved Reserved Reserved GPMC NAND
Reserved Reserved Reserved GPMC NOR
Reserved Reserved Reserved Reserved
SFDP Read Cmd Mode xSPI
Reserved ARM/Thumb No/Dev No boot/Dev Boot

BOOT-MODE[13] – These pins provide optional settings and are used in conjunction with the backup boot device devices. Switch SW4.6 when ON sets 1 and sets 0 if OFF, see the device-specific TRM.

BOOT-MODE [14:15] – Reserved. Provides backup boot media configuration options.

Table 2-22 Backup Boot Media Configuration BOOT-MODE[13]
SW4.6 Boot Device
Reserved None
Mode USB
Reserved Reserved
Reserved UART
IF Ethernet
Port MMC/SD
Reserved SPI
Reserved I2C
Table 2-23 Serial NAND Configuration Fields
BOOTMODE Pins Field Value Description
8 [SW5.1] Read Mode 2 0 Reserved (Read mode is taken from Read Mode 1
1

SPI/ 1-1-1 mode (Read mode is taken from Read

Mode 2 and Read Mode 1 is ignored)
7 [SW3.8] Read Mode 1 0 OSPI/ 1-1-8 Mode (valid only when Read Mode 2 is 0)
1 OSPI/ 1-1-4 Mode (valid only when Read Mode 2 is 0)
Table 2-24 OSPI Boot Configuration Fields
BOOTMODE Pins Field Value Description
8 [SW5.1] Iclk 0 Iclock source external
1 Iclock source internal (pad loopback)
7 [SW3.8] Csel 0 Boot Flash is on CS 0
1 Boot Flash is on CS 1
Table 2-25 QSPI Boot Configuration Fields
BOOTMODE Pins Field Value Description
8 [SW5.1] Iclk 0 Iclock source external
1 Iclock source internal (pad loopback)
7 [SW3.8] Csel 0 Boot Flash is on CS 0
1 Boot Flash is on CS 1
Table 2-26 SPI Boot Configuration Fields
BOOTMODE Pins Field Value Description
8 [SW4.1] Mode 0 SPI Mode 0
1 SPI Mode 3
7 [SW3.8] Csel 0 Boot Flash is on CS 0
1 Boot Flash is on CS 1
Table 2-27 Ethernet RGMII Boot Configuration Fields
BOOTMODE Pins Field Value Description
9 [SW4.2] Clkout 0 25MHz clock not generated on CLKOUT0
1 25MHz clock generated on CLKOUT0
8 [SW4.1] Delay 0 Must be set to 0 for RGMII with internal Tx delay
1 Reserved
7 [SW3.8] Link info 0 MDIO PHY scan used for link parameters
1 Link parameters programmed by the ROM
Table 2-28 Ethernet RMII Boot Configuration Fields
BOOTMODE Pins Field Value Description
9 [SW4.2] Clkout 0 50MHz clock not generated on CLKOUT0
1 50MHz clock generated on CLKOUT0
8 [SW4.1] Clk src 0 External clock source for RMII1_REF_CLK
1 Internal clock source for RMII1_REF_CLK
7 [SW3.8] RMII 0 This bit must be set to 0
1 Reserved
Table 2-29 Ethernet RMII Clocking
BOOTMODE Pin 9 (Clk out) BOOTMODE Pin 8 (Clk src) Description
0 0 50MHz external source to RMII_REF_CLK and to external Ethernet PHY input clock (CLKOUT0 is unused) These are the recommended settings
0 1 Not a valid configuration
1 0 CLKOUT0 is configured to 50MHz and connect to both RMII1_REF_CLK and to external Ethernet PHY input clock
1 1 Not a valid configuration
Table 2-30 Ethernet Backup Boot Configuration Field
BOOTMODE Pins Field Value Description
13 [SW4.2] Interface 0 RGMII with internal TX delay
1 RMII with external clock source
Table 2-31 I2C Boot Configuration Fields
BOOTMODE Pins Field Value Description
9 [SW4.2] Bus reset 0 Hung bus reset attempt after 1ms
1 No hung bus reset attempted
7 [SW3.8] Address 0 EEPROM's address is 0x50
1 EEPROM's address is 0x51
Table 2-32 SD Card Boot Configuration Fields
BOOTMODE Pins Field Value Description

9 [SW4.2]

13(1) [SW4.2]

 Port 0 Reserved
1 MMC Port 1 (4 bit width). This bit must be set to 1
7 [SW3.8] FS/Raw 0 Filesystem mode
1 Raw Mode
(1) When MMCSD is the backup mode
Table 2-33 eMMC Boot Configuration Fields
BOOTMODE Pins Field Value Description

9 [SW4.2]

13(1) [SW4.2]

 Port 0 MMCSD Port 0 (8 bit width). This bit must be set to 0
1 Reserved
7 [SW3.8] FS/Raw 0 Filesystem mode
1 Raw Mode
(1) When MMCSD is the backup mode
Table 2-34 USB Boot Configuration Fields
BOOTMODE Pins Field Value Description
9 [SW4.2] Core Voltage 0 0.85V core voltage
1 0.75V core voltage

8 [SW4.1]

13(1) [SW4.2]

 Mode 0 DFU (USB device firmware upgrade)
1 Host (MSC boot)
7 [SW3.8] Lane Swap 0 D+/D- lines are not swapped
1 D+/D- lines are swapped
(1) When USB is the backup mode.
Table 2-35 xSPI Boot Configuration Fields
BOOTMODE Pins Field Value Description
9 [SW4.2] SFDP 0 SFDP disabled
1 SFDP enabled
8 [SW4.1] Read cmd 0 0x0B Read Command
1 0xEE Read Command
7 [SW3.8] Mode 0 1S-1S-1S mode @ 50MHz
1 8D-8D-8D mode @ 25MHz