SPRUJ51A June   2023  – November 2025

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Device Information
    4. 1.4 EVM Revisions and Assembly Variants
    5. 1.5 Specification
  6. 2Hardware
    1. 2.1  Additional Images
    2. 2.2  Key Features
      1. 2.2.1 Processor
      2. 2.2.2 Memory
      3. 2.2.3 JTAG Emulator
      4. 2.2.4 Supported Interfaces and Peripherals
      5. 2.2.5 Expansion Connectors Headers to Support Application Specific Add On Boards
    3. 2.3  Power
      1. 2.3.1 Power Requirements
      2. 2.3.2 Power Input
      3. 2.3.3 Power Supply
      4. 2.3.4 Power ON OFF Procedures
        1. 2.3.4.1 Power-On Procedure
        2. 2.3.4.2 Power-Off Procedure
        3. 2.3.4.3 Power Test Points
      5. 2.3.5 Power Sequencing
      6. 2.3.6 AM62x 17x17 SoC Power
      7. 2.3.7 Current Monitoring
    4. 2.4  AM62x-Low Power SK EVM Interface Mapping
    5. 2.5  Clocking
    6. 2.6  Reset
    7. 2.7  OLDI Display Interface
    8. 2.8  CSI Interface
    9. 2.9  Audio Codec Interface
    10. 2.10 HDMI Display Interface
    11. 2.11 JTAG Interface
    12. 2.12 Test Automation Header
    13. 2.13 UART Interface
    14. 2.14 USB Interface
      1. 2.14.1 USB2.0 Type A Interface
      2. 2.14.2 USB2.0 Type C Interface
    15. 2.15 Memory Interfaces
      1. 2.15.1 LPDDR4 Interface
      2. 2.15.2 OSPI
      3. 2.15.3 MMC Interfaces
        1. 2.15.3.1 MMC0 - eMMC Interface
        2. 2.15.3.2 MMC1 - Micro SD Interface
        3. 2.15.3.3 MMC2 - M2 Key E Interface
      4. 2.15.4 EEPROM
    16. 2.16 Ethernet Interface
      1. 2.16.1 CPSW Ethernet PHY1 Default Configuration
      2. 2.16.2 CPSW Ethernet PHY2 Default Configuration
    17. 2.17 GPIO Port Expander
    18. 2.18 GPIO Mapping
    19. 2.19 AM62x-Low Power SK EVM User Setup and Configuration
      1. 2.19.1 EVM DIP Switches
      2. 2.19.2 Boot Modes
      3. 2.19.3 User Test LEDs
    20. 2.20 Expansion Headers
      1. 2.20.1 User Expansion Connector
      2. 2.20.2 MCU Connector
      3. 2.20.3 PRU Connector
    21. 2.21 Push Buttons
    22. 2.22 I2C Address Mapping
  7. 3Hardware Design Files
  8. 4Compliance Information
    1. 4.1 EMC, EMI and ESD Compliance
  9. 5Additional Information
    1. 5.1 Known Issues and Modifications
    2.     Trademarks
    3.     72
  10. 6Revision History

2.16.1 CPSW Ethernet PHY1 Default Configuration

The default configuration of the DP83867 is determined using a number of resistor pull-up and pull-down values on specific pins of the PHY. Depending on the values installed, each of the configuration pins can be set to one of four modes by using the pull up and pull down options provided. The AM62x-Low Power SK EVM uses the 48-pin QFN package which supports the RGMII interface.

The DP83867 PHY uses four level configurations based on resistor strapping which generate four distinct voltage ranges. The resistors are connected to the RX data and control pins which are normally driven by the PHY and are inputs to the processor. The voltage range for each mode is shown below:

  • Mode1 – 0V to 0.3V
  • Mode 2 – 0.462V to 0.6303V
  • Mode3 – 0.7425V to 0.9372V
  • Mode4 – 2.2902V to 2.9304V

Footprints for both pull-up and pull-down is provided on all the strapping pins except LED_0. LED_0 is for Mirror Enable, which is set to mode 1 by default, Mode 4 is not applicable and Mode2, Mode3 option is not desired.CPSW_RGMII1 port of the AM62X 17x17 SoC is connected to DP83867 whose configuration is as given below:

  • PHY ADDR: 00000
  • Auto_neg: Disabled
  • ANG_sel: 10/100/1000
  • RGMIIClk skew Tx: 0ns
  • RGMIIClk skew Rx: 2ns
Table 2-13 CPSW Ethernet PHY–1 Strap values
Strap Setting Pin Name Strap Function Mode Valueof Strap Function Description
PHY Address RX_D2 PHY_AD3 1 0 PHY Address: 0000
PHY_AD2 1 0
RX_D0 PHY_AD1 1 0
PHY_AD0 1 0
Auto Negotiation RX_DV/ RX_CTRL Auto- neg 3 0 Autoneg Disabled
Modes of Operation LED2 RGMIIClock Skew TX[1] 5 0 RGMIITX Clock Skew is set to 0ns
RGMIIClock Skew TX[0] 5 0
LED_1 RGMIIClock Skew TX[2] 5 1
ANEG_SEL 1 0 advertiseability of 10/100/1000
LED_0 Mirror Enable 1 0 Mirror Enable Disabled
GPIO_1 RGMIIClock Skew RX[2] 1 0 RGMIIRX Clock Skew is set to 2ns
RGMIIClock Skew RX[1] 1 0
GPIO_0 RGMIIClock Skew RX[0] 1 0