SPRUJ59 April   2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Feature Differences Between F28003x and F28P55x
    1. 1.1 F28003x and F28P55x Feature Comparison
  5. 2PCB Hardware Changes
    1. 2.1 PCB Hardware Changes for the 100-Pin PZ, 80-Pin PNA and 64-Pin PM Packages
    2. 2.2 100-Pin PZ, 80-Pin PNA and 64-Pin PM Migration Between F28003x and F28P55x For New and Existing PCB
    3. 2.3 GPIO Input Buffer Control Register
  6. 3Feature Differences for System Consideration
    1. 3.1 New Features in F28P55x
      1. 3.1.1 Programmable Gain Amplifier(PGA)
      2. 3.1.2 Universal Serial Bus (USB)
      3. 3.1.3 5V Failsafe IOs
    2. 3.2 Communication Module Changes
    3. 3.3 Control Module Changes
    4. 3.4 Analog Module Differences
    5. 3.5 Other Device Changes
      1. 3.5.1 PLL
      2. 3.5.2 PIE Channel Mapping
      3. 3.5.3 Bootrom
      4. 3.5.4 SW Libraries Included in the ROM
      5. 3.5.5 AGPIO
    6. 3.6 Power Management
      1. 3.6.1 LDO/VREG
      2. 3.6.2 POR/BOR
      3. 3.6.3 Power Consumption
    7. 3.7 Memory Module Changes
    8. 3.8 GPIO Multiplexing Changes
    9. 3.9 Analog Multiplexing Changes
  7. 4Application Code Migration From F28003x to F28P55x
    1. 4.1 C2000Ware Header Files
    2. 4.2 Linker Command Files
    3. 4.3 C2000Ware Examples
  8. 5Specific Use Cases Related to F28P55x New Features
    1. 5.1 PGA
    2. 5.2 USB
  9. 6EABI Support
    1. 6.1 Flash API
  10. 7References

3.4 Analog Module Differences

This section outlines the analog differences between F28003x and F28P55x. Three Programmable Gain Amplifiers(PGA) are a new addition to the F28P55x and there are now five ADCs vs the 3 ADCs on the F28003x device. There are several enhancements inside the CMPSS and ADC modules.

Table 3-3 Analog Module Differences
Module Category F28003x F28P55x Notes
Analog Sysctrl HW Changes - Global Sychronous SW Trigger for ADC Allows for SW Trigger to ADC sent to selected ADCs simultaneously
- New register for VREFHI selection Support for per ADC VREFHI selection reference voltage:
  1. Internal VREFHI
  2. External VREFHI
  3. VDDA
- New register for VREFHI selection Support for per ADC VREFLO selection reference voltage:
  1. VREFLO pin
  2. VSSA
- Support for full 3.3V FSR with External VREFHI Can supply 1.65V on VREFHI in external mode to have FSR = 3.3V
- 12mA Drive on Select GPIOs For compatiblity with I2C and PMBUS High Speed + mode, GPIO 2/3/9/32 have option for 12mA drive strength
- 1.35V VIH compatibility on select GPIOs Changes VIH for GPIO 2/3/9/32 to 1.35V
Register ANAREFCTL.ANAREFSEL ANAREFPCTRL.REFPMUXSELx x = ADC A/B/C/D/E Each ADC is now configured independently for VREFHI source
- ANAREFNCTL.REFNMUXSELx x = ADC A/B/C/D/E Each ADC has VREFLO selection capability
ANAREFCTL.ANAREF2P5SEL ANAREFPCTL.ANAREFx1P65SEL x = ADC A/B/C/D/E Each ADC has independent 1.65V(3.3V FSR) or 2.5V FSR selection. Also effects external reference mode.
- IO_DRVSEL Configure selected GPIO (IOL) drive strength for either 4mA(default) or 12mA (IOL)
- IO_MODESEL Configure selected GPIO VIH to either 3.3V(default) or 1.35V
ADC1 Number 3 - ADCA, ADCB, ADCC 5 - ADCA, ADCB, ADCC, ADCD, ADCE F28003x has Type 5 ADC
F28P55x has Type 6 ADC
Max Speed 60 MHz 75MHz Max throughput is

3.9MSPS on the F28P55x vs 4MSPS on the F28003x device
HW Changes - New PPB features
  1. Summing/Max/Min/Abs value
  2. Oversampling Support w repeat block
  3. Previous Conversion Delta
  4. Output Filtering
  1. Ability for PPB to Sum/Max/Min/Abs value of concurrent results
  2. Automatically aggregates and averages user defined number of samples, returns only the average to a result register. Used with ADC Repeater Block
  3. Compares last conversion to current conversion and generates corresponding action
  4. Returns values that are in range of filter window only, discarding others.
- ADC Repeater Logic Ability to initiate subsequent triggers automatically, with option to add phase delay. Can use with PPB to realize oversampling without CPU overhead
- Global SW Force SOC Trigger Ability to initiate a SW SOC trigger to all ADCs simultaneously
- ADC S/H Cap Reset Ability to reset the S/H Cap to VSSA between samples
Register ADCTL1 ADCTL1 Addition of External Mux Control and DMA Trigger Timings
ADCSOCxCTL.TRIGSEL ADCSOCxCTL.TRIGSEL Increased Trigger Options for ePWM and repeat block support
INTFLGCLR ADCINTFLGCLR
ADCINTSOCSEL2 ADCINTSOCSEL1 All SOC interrupt triggers moved to INTSOCSEL1
GPDAC Number 2 - GPDACA, GPDACB 1- GPDACA Type 1 GPDAC on both devices
CMPSS1 Number 4 - CMPSS1 to CMPSS4 4 - CMPSS1 to CMPSS4 F28003x has Type 2 CMPSS
F28P55x has Type 6 CMPSS
HW changes
  1. Added DAC Ramp Generator to Low Side Comparator
  2. Ramp Generator includes up ramp support
  3. CMPSS1 can bring out its low side DAC to pin as DACB2
Registers RAMPMAXREFA RAMPHREFA Register Name Change
RAMMAXREFS RAMPHREFS Register Name Change
RAMPDECVALA RAMPHSTEPVALA Register Name Change
RAMPDECVALS RAMPHSTEPVALS Register Name Change
RAMPSTS RAMPHSTS Register Name Change
RAMPDLYA RAMPHDLYA Register Name Change
RAMPDLYS RAMPHDLYS Register Name Change
CTRIPLFILCTL CTRIPLFILCTL - Field Changes Additions and changes to fields within this register. For more details, see the device-specific TRMs.
CTRIPLFILCLKCTL CTRIPLFILCLKCTL - Field Changes Increased prescalar range
CTRIPHFILCTL CTRIPHFILCTL - Field Changes Additions and changes to fields within this register. For more details, see the device-specific TRMs.
CTRIPHFILCLKCTL CTRIPHFILCLKCTL - Field Changes Increased prescalar range
- COMPDACLCTL Register and functionality added to support dual ramp generators
- RAMPLREFA Register and functionality added to support dual ramp generators
- RAMPLREFS Register and functionality added to support dual ramp generators
- RAMPLSTEPVALA Register and functionality added to support dual ramp generators
- RAMPLSTEPVALS Register and functionality added to support dual ramp generators
- RAMPLSTS Register and functionality added to support dual ramp generators
- RAMPLDLYA Register and functionality added to support dual ramp generators
- RAMPLDLYS Register and functionality added to support dual ramp generators
- CTRIPLFILCLKCTL2 Register and functionality added to support dual ramp generators
- CTRIPHFILCLKCTL2 Register and functionality added to support dual ramp generators
Temp Sensor Number 1 - (in ADCC ch 12) 1 - (in ADCC ch12)
  1. In porting software from F28003x to F28P55x (or the other way around), care must be taken to ensure that the correct ADC channels are used because of a difference in channel assignment, see Analog Multiplexing Changes.
  2. Use of DACL from CMPSS1 and normal CMPSS1 fucntion are mutually exclusive.