SPRUJ59 April   2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Feature Differences Between F28003x and F28P55x
    1. 1.1 F28003x and F28P55x Feature Comparison
  5. 2PCB Hardware Changes
    1. 2.1 PCB Hardware Changes for the 100-Pin PZ, 80-Pin PNA and 64-Pin PM Packages
    2. 2.2 100-Pin PZ, 80-Pin PNA and 64-Pin PM Migration Between F28003x and F28P55x For New and Existing PCB
    3. 2.3 GPIO Input Buffer Control Register
  6. 3Feature Differences for System Consideration
    1. 3.1 New Features in F28P55x
      1. 3.1.1 Programmable Gain Amplifier(PGA)
      2. 3.1.2 Universal Serial Bus (USB)
      3. 3.1.3 5V Failsafe IOs
    2. 3.2 Communication Module Changes
    3. 3.3 Control Module Changes
    4. 3.4 Analog Module Differences
    5. 3.5 Other Device Changes
      1. 3.5.1 PLL
      2. 3.5.2 PIE Channel Mapping
      3. 3.5.3 Bootrom
      4. 3.5.4 SW Libraries Included in the ROM
      5. 3.5.5 AGPIO
    6. 3.6 Power Management
      1. 3.6.1 LDO/VREG
      2. 3.6.2 POR/BOR
      3. 3.6.3 Power Consumption
    7. 3.7 Memory Module Changes
    8. 3.8 GPIO Multiplexing Changes
    9. 3.9 Analog Multiplexing Changes
  7. 4Application Code Migration From F28003x to F28P55x
    1. 4.1 C2000Ware Header Files
    2. 4.2 Linker Command Files
    3. 4.3 C2000Ware Examples
  8. 5Specific Use Cases Related to F28P55x New Features
    1. 5.1 PGA
    2. 5.2 USB
  9. 6EABI Support
    1. 6.1 Flash API
  10. 7References

2.3 GPIO Input Buffer Control Register

The F28P55x replaces a pair of VDDIO/VDD pins with GPIOs. When migrating from the F28003x it is necessary to disable the input buffer on the what was the VDD pin, so that the GPIO is not improperly driven(assuming the connection to VDD persists). The GPIOINENACTRL register disables the input buffer when cleared to 0. The default state at reset of this register is a 1, which enables the input buffer of the corresponding GPIO. The other GPIO can be safely connected to VDDIO, but if desired the input buffer can also be disabled on the corresponding GPIO if there are noise concerns in the system.

This address exists within the analog subsystem registers, which has a base address of 0x0005 D700. The GPIO input buffer control register (GPIOINENACTRL) has an offset of 0x132, within the analog subsystem base address.

Table 2-2 GPIOINENACTRL Register Field Descriptions
Bit Field Type Reset Description
31-4 RESERVED R 0h Reserved
3 GPIO63 R/W 1h One time configuration for GPIO63 to decide whether Input buffer (INENA control) is enabled or disabled
0 - Input buffer is disabled
1 - Input buffer is enabled
Reset type: XRSn
2 GPIO62 R/W 1h One time configuration for GPIO62 to decide whether Input buffer (INENA control) is enabled or disabled
0 - Input buffer is disabled
1 - Input buffer is enabled
Reset type: XRSn
1 GPIO21 R/W 1h One time configuration for GPIO21 to decide whether Input buffer (INENA control) is enabled or disabled
0 - Input buffer is disabled
1 - Input buffer is enabled
Reset type: XRSn
0 GPIO20 R/W 1h One time configuration for GPIO20 to decide whether Input buffer (INENA control) is enabled or disabled
0 - Input buffer is disabled
1 - Input buffer is enabled
Reset type: XRSn