SPRUJE8C December 2024 – June 2025 AM2752-Q1 , AM2754-Q1
The AM275x SoC features a single MMC0 port (MMC0). MMC0 can be routed to either an eMMC Flash (MTFC32GAZAQHD-IT) or a Micro SD Card connector (MEM2052-00-195-00-A) through a 1:2 FET Switch (TS3DDR3812RUAR). MMC0 routing direction is determined by the MMC0_SEL_3V3 signal tied to the SELx pins of the FET Switch. MMC0_SEL_3V3 signal state (High or Low) is controlled by SW9 as shown in Figure 2-19.
| MMC0_SEL_3V3 | MMC0 | VDDSHV5 IO Voltage | SW9 Position |
|---|---|---|---|
| 0 | Micro SD interface | 3.3V | ON |
| 1 | eMMC interface | 1.8V | OFF |
The AM275x EVM features a 32GB eMMC Flash memory (MTFC32GAZAQHD-IT), to which MMC0 can be routed to when SW9 (Figure 2-19) is OFF.
The eMMC Flash is a communication and mass data storage device that includes a Multimedia Card (MMC) interface and a NAND Flash component.
The AM275x SoC MMC0 Interface supports High Speed Double Data Rates (DDR) up to 50MHz or 100MBps when routed to the eMMC Flash. The AM275x EVM features the option to populate external pull-up resistors on data lines eMMC0_D[1:7] to prevent bus floating. A series resistor close to the AM275X SoC is provided for the clock signal MMC0_CLK for signal integrity.
The eMMC Flash is powered by 3.3V (VCC_3V3_SYS) for NAND Memory and 1.8V (VCC1V8_SYS) for the eMMC Interface. The MMC0 I/O group is powered by the VDDSHV5 power domain, which is connected to 1.8V IO supply (SW9 OFF).
The eMMC Flash requires an active low reset from the host. By default, the hardware reset function is temporarily disabled in the eMMC Flash. The host must set ECSD register byte 162, bits [1:0] to 0x1 to enable this functionality before the host can use it. External Reset is provided by ANDing RESETSTATz from the AM275x SoC, and the eMMC specific reset signal GPIO_eMMC_RSTn from the 1.8V I/O Expander.
Additionally, MMC0 can be routed to a Micro SD card connector (MEM2052-00-195-00-A) when SW9 (Figure 2-19) is ON.
The AM275x SoC MMC0 Interface supports Ultra High-Speed Phase I (UHS_I) operation when routed to the Micro SD card.
The Micro SD card interface is set to operate in SD mode by default. For high-speed cards, the ROM Code of the AM275x SoC attempts to find the fastest speed that the card and the controller can support, then transition to 1.8V I/O through the VSEL_SD_SoC signal from the AM275x SoC.