SPRUJG0B December   2024  – November 2025 F29H850TU , F29H859TU-Q1

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Performance Optimization
    1. 2.1 Compiler Settings
      1. 2.1.1 Enabling Debug and Source Inter-Listing
      2. 2.1.2 Optimization Control
      3. 2.1.3 Floating-Point Math
      4. 2.1.4 Fixed-Point Division
      5. 2.1.5 Single vs Double Precision Floating-Point
      6. 2.1.6 Link-Time Optimization (LTO)
    2. 2.2 Memory Settings
      1. 2.2.1 Executing Code From RAM
      2. 2.2.2 Executing Code From Flash
      3. 2.2.3 Data Placement
    3. 2.3 Code Construction and Configuration
      1. 2.3.1 Inlining
      2. 2.3.2 Intrinsics
      3. 2.3.3 Volatile Variables
      4. 2.3.4 Function Arguments
      5. 2.3.5 Enabling Wider Data Accesses
      6. 2.3.6 Auto Code-Generation Tools
      7. 2.3.7 Accurately Profiling Code
    4. 2.4 Application Code Optimization
      1. 2.4.1 Optimized SDK Libraries
      2. 2.4.2 Optimizing Code-Size With Libraries
      3. 2.4.3 C29 Special Instructions
      4. 2.4.4 C29 Parallelism
      5. 2.4.5 32-Bit Variables and Writes Preferred
      6. 2.4.6 Coding Style and Impact on Performance
  6. 3References
  7. 4Revision History

2.2.1 Executing Code From RAM

To understand which RAMs are 0 wait-state access for Program code for C29 CPUs, see the Memory Subsystem (MEMSS) chapter of the F29H85x and F29P58x Real-Time Microcontrollers Technical Reference Manual. As an example, CPU1 and CPU2 have 0-WS access for program code on LPAx RAM. CPU1 and CPU3 have 0-WS access for program code on CPAx RAM.

Functions that need to execute from RAM can be placed in a RAM section, and the linker command file can be used to control the copy of this function to RAM at boot time. More information can be found here.

Source file:
__attribute__((section(“ramfunc”), noinline)) void foo() {.. }
Linker command file:
ramfunc : load=FLASH, run=RAM, table(BINIT)