SPRZ536A september   2022  – june 2023 AM69 , AM69A , TDA4AH-Q1 , TDA4AP-Q1 , TDA4VH-Q1 , TDA4VP-Q1

 

  1.   1
  2. 1Modules Affected
  3. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  4. 3Silicon Revision 1.0 Usage Notes and Advisories
    1. 3.1 Silicon Revision 1.0 Usage Notes
      1.      i2134
    2. 3.2 Silicon Revision 1.0 Advisories
      1.      i2049
      2.      i2062
      3.      i2063
      4.      i2064
      5.      i2065
      6.      i2079
      7.      i2097
      8.      i2102
      9.      i2120
      10.      i2134
      11.      i2137
      12.      i2146
      13.      i2157
      14.      i2159
      15.      i2160
      16.      i2161
      17.      i2163
      18.      i2166
      19.      i2177
      20.      i2189
      21.      i2190
      22.      i2196
      23.      i2197
      24.      i2205
      25.      i2215
      26.      i2216
      27.      i2219
      28.      i2232
      29.      i2234
      30.      i2242
      31.      i2244
      32.      i2245
      33.      i2249
      34.      i2253
      35.      i2271
      36.      i2272
      37.      i2278
      38.      i2279
      39.      i2310
      40.      i2311
      41.      i2312
      42.      i2320
      43.      i2326
      44.      i2351
      45.      i2362
      46.      i2366
      47.      i2371
      48.      i2372
      49.      i2378
      50.      i2381
      51.      i2383
  5.   Trademarks
  6.   Revision History

i2049


ECC_AGGR: Potential IP Clockstop/Reset Sequence Hang due to Pending ECC Aggregator Interrupts

Details:

The ECC Aggregator module is used to aggregate safety error occurrences (which are rare) and generate interrupts to notify software. The ECC Aggregator provides software control over the enabling/disabling and clearing of safety errors interrupts.

When software is performing a clockstop/reset sequence on an IP, the sequence can potentially not complete because the IP's associated ECC Aggregator instance is not idle. The ECC Aggregator idle status is dependent upon any pending safety error interrupts either enabled or disabled, which have not been cleared by software. As a result, the IP's clockstop/reset sequence may never complete (hang) if there are any pending safety errors interrupts that remain uncleared.

Workaround(s):

General Note:

Clockstopping the ECC Aggregator is not supported in functional safety use-cases.

Software should use the following workaround for non-functional safety use-cases:

  1. Enable all ECC Aggregator interrupts for the IP
  2. Service and clear all Pending interrupts
  3. Step 3:
    1. Disable all interrupt sources to the ECC Aggregator, followed by performing Clockstop/reset sequence.
    2. Perform Clockstop/reset sequence, while continuing to service/clear pending interrupts.

Due to interrupts being external stimuli, software has two options for step 3:

  1. Disable all interrupt sources (EDC CTRL checkers) that can generate pending ECC_AGGR interrupts prior to performing the clockstop/reset sequence
  2. Continue to service/clear pending interrupts that occur while performing the clkstop/reset sequence. The sequence would proceed when all interrupts are cleared.

Software in general may need to detect pending interrupts that continuously fire during this entire sequence (ex. in the case of a stuck-at fault scenario), and disable their associated EDC CTRL safety checkers to allow the clockstop/reset sequence to progress towards completion.