SPRZ572 April   2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1

 

  1.   1
  2.   TMS320F28003x Real-Time MCUs Silicon ErrataSilicon Revision 0
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development-Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision 0 Usage Notes and Advisories
    1. 3.1 Silicon Revision 0 Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 Caution While Using Nested Interrupts
      3. 3.1.3 Security: The primary layer of defense is securing the boundary of the chip, which begins with enabling JTAGLOCK and Zero-pin Boot to Flash feature
    2. 3.2 Silicon Revision 0 Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8. 3.2.1 Advisory
      9.      Advisory
      10. 3.2.2 Advisory
      11.      Advisory
      12. 3.2.3 Advisory
      13.      Advisory
      14.      Advisory
      15.      Advisory
      16. 3.2.4 Advisory
      17.      Advisory
      18. 3.2.5 Advisory
      19.      Advisory
      20.      Advisory
      21.      Advisory
      22.      Advisory
  6. 4Documentation Support
  7. 5Trademarks
  8. 6Revision History

Advisory

GPIO: 5V Signal Cannot Drive Low When 20mA Drive Mode is Enabled for Select GPIOs

Revisions Affected

0

Details

GPIOs 2, 3, 9, and 32 have support for 5V level TTL signals, and also have a selectable drive strength (either 4mA or 20mA) in order to enable fast plus mode for PMBUS communications. This is controlled with the DRIVESEL bit in the IO_DRVSEL register in the analog subsystem module. If the voltage on the GPIO pin is above VDDIO + 0.3V and the DRIVESEL bit = 1, then the GPIO will not be able to drive the pin to a logical low.

Workaround

If the voltage level on the GPIOs in question is kept to VDDIO + 0.3V or below, there is no impact to the functional behavior of the device. If voltage levels at the pin are above VDDIO + 0.3V, then the DRIVESEL bit should be set to "0", disabling the higher drive strength to the GPIO. In this scenario, fast plus mode is no longer supported; and the max clock rate of the PMBUS is 400kHz, supporting fast mode only.