SWRA574B October   2017  – February 2020 AWR1243 , AWR2243

 

  1.   AWR2243 Cascade
    1.     Trademarks
    2. 1 Cascaded AWR2243 System
    3. 2 Synchronization of AWR2243 Chips
      1. 2.1 20 GHz (FMCW) RF LO Sync
      2. 2.2 Digital Frame Sync
        1. 2.2.1 Frame (Burst) and Chirp Timing in AWR2243
        2. 2.2.2 Frame (Burst) and Chirp Timing in a Cascaded System
        3. 2.2.3 Inter Chip Imbalance of Digital Sync Timing
      3. 2.3 40 MHz (System) Reference Clock Synchronization
    4. 3 Connectivity
      1. 3.1 20 GHz LO Sync Pins Connectivity
      2. 3.2 DIG_SYNC Connectivity
      3. 3.3 40 MHz (System) Reference Clock Connectivity
    5. 4 20 GHz LO Sync Link Budget
    6. 5 Software Messaging
      1. 5.1 Configuration of Devices
      2. 5.2 Configuration of Frames
        1. 5.2.1 Similar Configuration Across AWR2243 Devices
        2. 5.2.2 Dissimilar Configuration Across AWR2243 Devices
      3. 5.3 Triggering of Frames
      4. 5.4 Example Usage
      5. 5.5 Other Usages
    7. 6 Advantages of AWR2243 Cascading System
    8. 7 References
  2.   Revision History

6 Advantages of AWR2243 Cascading System

The AWR2243 cascaded solution presented in this application report offers many key advantages.

The AWR2243 integrates 20 GHz PA (power amplifier) and LNA (low-noise amplifier) along the LO path that eliminates the need for discrete PA and LNA along the PCB transmission lines. Each AWR2243 device incorporates separate 20 GHz PA for each LO output path (one PA for FMCW_CLKOUT and another for FMCW_SYNCOUT) and separate LNA for each internal branch of the FMCW_SYNCIN1/2 LO input path. The 20 GHz LO routing on the PCB can be minimized through use of the multiple FMCW_CLKOUT/SYNCOUT LO output ports and FMCW_SYNCIN1/2 LO input ports, which are both located on opposite sides of the BGA. Further, the frequency for on board LO routing has been optimally chosen. Routing the 20 GHz LO instead of the 80 GHz mmWave signal on board enables minimizing of board routing loss, noise and cost.

Although only a few topologies of two chip and four chip cascading have been illustrated these examples can be extended to cascaded systems using more than four chips. Overall, the features explained here enable design and manufacturing of a high performance radar system with low cost, size and power consumption.