SWRA574B October   2017  – February 2020 AWR1243 , AWR2243

 

  1.   AWR2243 Cascade
    1.     Trademarks
    2. 1 Cascaded AWR2243 System
    3. 2 Synchronization of AWR2243 Chips
      1. 2.1 20 GHz (FMCW) RF LO Sync
      2. 2.2 Digital Frame Sync
        1. 2.2.1 Frame (Burst) and Chirp Timing in AWR2243
        2. 2.2.2 Frame (Burst) and Chirp Timing in a Cascaded System
        3. 2.2.3 Inter Chip Imbalance of Digital Sync Timing
      3. 2.3 40 MHz (System) Reference Clock Synchronization
    4. 3 Connectivity
      1. 3.1 20 GHz LO Sync Pins Connectivity
      2. 3.2 DIG_SYNC Connectivity
      3. 3.3 40 MHz (System) Reference Clock Connectivity
    5. 4 20 GHz LO Sync Link Budget
    6. 5 Software Messaging
      1. 5.1 Configuration of Devices
      2. 5.2 Configuration of Frames
        1. 5.2.1 Similar Configuration Across AWR2243 Devices
        2. 5.2.2 Dissimilar Configuration Across AWR2243 Devices
      3. 5.3 Triggering of Frames
      4. 5.4 Example Usage
      5. 5.5 Other Usages
    7. 6 Advantages of AWR2243 Cascading System
    8. 7 References
  2.   Revision History

5.5 Other Usages

Although only some usages are explained in detail, minor variations are possible. They are briefly described here.

It is possible to trigger all AWR2243 devices (including the master) in HWTRIGGER mode. For this, the host needs to generate DIG_SYNC_IN pulses of the right periodicity and feed to DIG_SYNC_IN pins of all the chips (including the master).

Most of the above note is written using the basic frame configuration message, namely AWR_FRAME_CONF_SB, for easing the explanation. It is possible to use AWR_ADVANCED_FRAME_CONF_SB for achieving more advanced chirp or frame structures. In such a case, the DIG_SYNC_IN pulse occurs at the beginning of each burst (or sub frame or frame – to be determined). If such an advanced frame configuration is used in conjunction with SWTRIGGER of the master too, then the host needs to generate the pulses accordingly.