SWRA574B October   2017  – February 2020 AWR1243 , AWR2243

 

  1.   AWR2243 Cascade
    1.     Trademarks
    2. 1 Cascaded AWR2243 System
    3. 2 Synchronization of AWR2243 Chips
      1. 2.1 20 GHz (FMCW) RF LO Sync
      2. 2.2 Digital Frame Sync
        1. 2.2.1 Frame (Burst) and Chirp Timing in AWR2243
        2. 2.2.2 Frame (Burst) and Chirp Timing in a Cascaded System
        3. 2.2.3 Inter Chip Imbalance of Digital Sync Timing
      3. 2.3 40 MHz (System) Reference Clock Synchronization
    4. 3 Connectivity
      1. 3.1 20 GHz LO Sync Pins Connectivity
      2. 3.2 DIG_SYNC Connectivity
      3. 3.3 40 MHz (System) Reference Clock Connectivity
    5. 4 20 GHz LO Sync Link Budget
    6. 5 Software Messaging
      1. 5.1 Configuration of Devices
      2. 5.2 Configuration of Frames
        1. 5.2.1 Similar Configuration Across AWR2243 Devices
        2. 5.2.2 Dissimilar Configuration Across AWR2243 Devices
      3. 5.3 Triggering of Frames
      4. 5.4 Example Usage
      5. 5.5 Other Usages
    7. 6 Advantages of AWR2243 Cascading System
    8. 7 References
  2.   Revision History

2.2.1 Frame (Burst) and Chirp Timing in AWR2243

The AWR2243 device includes a frame reference counter (FRC) which maintains timing across frames (bursts). It generates a digital synchronization (labeled "Dig Sync" in Figure 5) signal, also referred to as frame (burst) start signal based on the frame (burst) timing parameters given by the API messages described in the Software Messaging section. The processor firmware also relies on the FRC to schedule calibrations, monitoring and setting up of functional bursts.

The AWR2243 device also includes a high speed synchronizer and clock gator, which starts off the high speed clocks to the RX ADCs and chirp timing engine in synchronism with Dig Sync. The chirp timing engine maintains the timing during and across multiple chirps within each frame (burst) and accounts for the generation of synthesizer ramp and RX ADC valid data picking, and so forth. At the end of each frame (burst), the clocks are stopped by the processor. This is illustrated in the timing and block diagrams below in single chip usage example.

fig6a.pngFigure 5. Frame (Burst) Timing and Clock Generation in AWR2243