TIDT320A january   2023  – july 2023

 

  1.   1
  2.   Description
  3.   Features
  4.   Applications
  5. 1Test Prerequisites
    1. 1.1 Voltage and Current Requirements
    2. 1.2 Functional Block Diagram
    3. 1.3 Pin Functions
  6. 2Waveforms
    1. 2.1 Switching Frequency and Operating Modes
    2. 2.2 Output Voltage Ripple
    3. 2.3 Load Transients
    4. 2.4 Start-Up Sequence
  7. 3Testing and Results
    1. 3.1 Efficiency Graphs
    2. 3.2 Efficiency Data
    3. 3.3 No Load and OFF State Power Consumption
    4. 3.4 Thermal Images
    5. 3.5 Bode Plots
    6. 3.6 Load Regulation

1.3 Pin Functions

Table 1-2 provides the functional descriptions of the pins.

Table 1-2 Pin Functional Descriptions
Pin Name Pin Number Description
12VSB J2: pins 3, 4, 6 Main 12-V output. The combination of 12VSB and S12V are capable of supplying up to 3.7 A. The 12VSB output is separated from the S12V output by back-to-back FET controlled by the TPS74800 ORing controller, allowing the 12VSB outputs from multiple supplies to be connected in parallel.
DIS J4: pin 14 Disable signal. This is an active-low, open-drain signal. Connecting this pin to PWRGND disables switching of the UCC28782 and turns off all outputs.
GND J2: pins 5, 7, 8 Return path for 12VSB and S12V and all secondary referenced circuits.
P18V J4: pin 20 Auxiliary 18-V output referenced to PWRGND. This output is capable of supplying up to 400 mA, but does require some minimum load on the 12VSB and S12V outputs to avoid abnormal operation. The P18V output voltage can range between 15 V and 18 V.
PWRGND J4: pins 7, 13, 19 Return path for VDCIN and all primary referenced circuits.
S12V J2: pin 2 Auxiliary 12-V output referenced to GND. The combination of 12VSB and S12V are capable of supplying up to 3.7 A.
VDCIN J4: pins 1, 2 DC input. Connect these pins to the input power source, normally the output of a PFC pre-regulator.