DLPS280 October   2024 DLPA3082

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 SPI Timing Parameters
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Description
    3. 6.3 Feature Description
      1. 6.3.1 Supply and Monitoring
        1. 6.3.1.1 Supply
        2. 6.3.1.2 Monitoring
          1. 6.3.1.2.1 Block Faults
          2. 6.3.1.2.2 Thermal Protection
      2. 6.3.2 DMD Supplies
        1. 6.3.2.1 LDO DMD
        2. 6.3.2.2 DMD HV Regulator
        3. 6.3.2.3 DMD/DLPC Buck Converters
        4. 6.3.2.4 DMD Monitoring
          1. 6.3.2.4.1 Power Good
          2. 6.3.2.4.2 Overvoltage Fault
      3. 6.3.3 Buck Converters
        1. 6.3.3.1 LDO Bucks
        2. 6.3.3.2 General Purpose Buck Converters
        3. 6.3.3.3 Buck Converter Monitoring
          1. 6.3.3.3.1 Power Good
          2. 6.3.3.3.2 Overvoltage Fault
        4. 6.3.3.4 Buck Converter Efficiency
      4. 6.3.4 Auxiliary LDOs
      5. 6.3.5 Measurement System
    4. 6.4 Device Functional Modes
    5. 6.5 Programming
      1. 6.5.1 SPI
      2. 6.5.2 Interrupt
      3. 6.5.3 Fast-Shutdown in Case of Fault
    6. 6.6 Register Maps
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Component Selection for General-Purpose Buck Converter
    3. 7.3 System Example with DLPA3082 Internal Block Diagram
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 Power-Up and Power-Down Timing
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
        1. 7.5.1.1 SPI Connections
      2. 7.5.2 Layout Example
      3. 7.5.3 Thermal Considerations
  9. 8 Device and Documentation Support
    1. 8.1 Third-Party Products Disclaimer
    2. 8.2 Device Support
      1. 8.2.1 Device Nomenclature
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

Over operating free-air temperature range. VIN = 12V, TA = 0 to +70°C, typical values are at TA = 25°C, Configuration according to Section 7.2 (VIN =12V) (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLIES
INPUT VOLTAGE
VIN Input voltage range VINA – pin 6(6) 12 20 V
VUVLO(7) UVLO threshold VINA falling (through a 5-bit trim function, 0.5V steps) 3.9 6.22 18.4 V
Hysteresis VINA rising 90 mV
VSTARTUP Startup voltage DMD_VBIAS, DMD_VOFFSET, DMD_VRESET loaded with 10mA 6 V
INPUT CURRENT
IIDLE Idle current IDLE mode, all VIN pins combined 15 µA
ISTD Standby current STANDBY mode, analog, internal supplies and LDOs enabled, DMD and BUCK CONVERTERS disabled. 3.7 mA
IQ_DMD Quiescent current (DMD) Quiescent current DMD block (in addition to ISTD), VINA + DRST_VIN 0.49 mA
IQ_BUCK Quiescent current
(per BUCK)		 Quiescent current per BUCK converter (in addition to ISTD), Normal mode, VINA + PWR_VIN + PWR1,2,6_VIN, PWR1,2,6_VOUT = 1V 4.3 mA
Quiescent current per BUCK converter (in addition to ISTD), Normal mode, VINA + PWR_VIN + PWR1,2,6_VIN, PWR1,2,6_VOUT = 5V 15
Quiescent current per BUCK converter (in addition to ISTD), Cycle-skipping mode, VINA + PWR_VIN + PWR1,2,6_VIN = 1V 0.41
Quiescent current per BUCK converter (in addition to ISTD), Cycle-skipping mode, VINA + PWR_VIN + PWR1,2,6_VIN = 5V 0.46
IQ_TOTAL Quiescent current (Total) Typical Application: ACTIVE mode, all VIN pins combined, DMD, and PWR1,2 enabled, PWR3,4,6 disabled. 38 mA
INTERNAL SUPPLIES
VSUP_5P5V Internal supply, analog 5 V
VSUP_2P5V Internal supply, logic 2.5 V
DMD — LDO DMD
VDRST_VIN 6 12 20 V
VDRST_5P5V 5.5 V
PGOOD Power good DRST_5P5V Rising 80%
Falling 60%
OVP Overvoltage protection DRST_5P5V 7.2 V
Regulator dropout At 25mA, VDRST_VIN= 5.5V 56 mV
Regulator current limit(2) 300 340 400 mA
DMD — REGULATOR
RDS(ON) MOSFET ON-resistance Switch A (from DRST_5P5V to DRST_HS_IND) 920 mΩ
Switch B (from DRST_LS_IND to DRST_PGND) 450
VFW Forward voltage drop Switch C (from DRST_LS_IND to DRST_VBIAS(1)), VDRST_LS_IND = 2V, IF = 100mA 1.21 V
Switch D (from DRST_LS_IND to DRST_VOFFSET(1)), VDRST_LS_IND = 2V, IF = 100mA 1.22
tDIS Rail Discharge time COUT= 1µF 40 µs
tPG Power-good timeout Not tested in production 15 ms
ILIMIT Switch current limit 610 mA
VOFFSET REGULATOR
VOFFSET Output voltage 10 V
DC output voltage accuracy IOUT= 10mA -0.3 0.3 V
DC Load regulation IOUT= 0mA to 10mA –10 V/A
DC Line regulation IOUT= 10mA, DRST_VIN = 8V to 20V –5 mV/V
VRIPPLE Output ripple IOUT= 10mA, COUT= 1µF 200 mVpp
IOUT Output current 0.1 10 mA
PGOOD Power-good threshold (fraction of nominal output voltage) VOFFSET rising 86%
VOFFSET falling 66%
C Output capacitor Recommended value(5) (use same value as output capacitor on VRESET) 1 µF
tDISCHARGE <40µs at VIN = 8V 1
VBIAS REGULATOR
VBIAS Output voltage 18 V
DC output voltage accuracy IOUT= 10mA –0.3 0.3 V
DC Load regulation IOUT= 0 to 10mA –18 V/A
DC Line regulation IOUT= 10mA, DRST_VIN = 8V to 20V –3 mV/V
VRIPPLE Output ripple IOUT= 10mA, COUT= 470nF 200 mVpp
IOUT Output current 0.1 10 mA
PGOOD Power-good threshold (fraction of nominal output voltage) VBIAS rising 86%
VBIAS falling 66%
C Output capacitor Recommended value(5) (use same or smaller value as output capacitors VOFFSET / VRESET) 470 nF
tDISCHARGE <40µs at VIN = 8V 470
VRESET REGULATOR
VRST Output voltage –14 V
DC output voltage accuracy IOUT= 10mA -0.3 0.3 V
DC Load regulation IOUT= 0 to 10mA –4 V/A
DC Line regulation IOUT= 10mA, DRST_VIN = 8 to 20V –2 mV/V
VRIPPLE Output ripple IOUT= 10mA, COUT= 1µF 120 mVpp
IOUT Output current 0.1 10 mA
PGOOD Power-good threshold 90%
C Output capacitor Recommended value(5) (use same value as output capacitor on VOFFSET) 1 µF
tDISCHARGE <40µs at VIN = 8V 1
DMD — BUCK CONVERTERS
OUTPUT VOLTAGE
VPWR_1_VOUT Output Voltage 0.8 V
VPWR_2_VOUT Output Voltage 1.8 V
DC output voltage accuracy IOUT= 0mA –3% 3%
MOSFET
RON,H High side switch resistance 25°C, VPWR_1,2_Boost – VPWR1,2_SWITCH = 5.5V 150 mΩ
RON,L Low side switch resistance(2) 25°C 85 mΩ
LOAD CURRENT
Allowed Load Current(3) 3 A
IOCL Current limit(2) LOUT= 3.3μH 3.2 3.6 4.2 A
ON-TIME TIMER CONTROL
tON On time VIN = 12V, VO = 5V 120 ns
tOFF(MIN) Minimum off time(2) TA = 25°C, VFB = 0V 270 ns
START-UP
Soft start 1 2.5 4 ms
PGOOD
RatioOV Overvoltage protection 120%
RatioPG Relative power good level Low to high 72%
BUCK CONVERTERS — LDO_BUCKS
VPWR_VIN Input voltage range PWR1,2,6_VIN 6 12 20 V
VPWR_5P5V PWR_5P5V 5.5 V
PGOOD Power good PWR_5P5V Rising 80%
Falling 60%
OVP Overvoltage Protection PWR_5P5V 7.2 V
Regulator dropout At 25mA, VPWR_VIN= 5.5V 41 mV
Regulator current limit(2) 300 340 400 mA
BUCK CONVERTER — GENERAL PURPOSE BUCK CONVERTER(8)
OUTPUT VOLTAGE
VPWR6_VOUT Output Voltage (General Purpose Buck2) 8-bit programmable 1 5 V
DC output voltage accuracy IOUT= 0mA –3.5% 3.5%
MOSFET
RON,H High side switch resistance 25°C, VPWR6_Boost – VPWR6_SWITCH = 5.5V 150 mΩ
RON,L Low side switch resistance(2) 25°C 85 mΩ
LOAD CURRENT
Allowed Load Current PWR6(3). 2 A
IOCL Current limit(2)(3) LOUT= 3.3μH 3.2 3.6 4.2 A
ON-TIME TIMER CONTROL
tON On time VIN = 12V, VO = 5V 120 ns
tOFF(MIN) Minimum off time(2) TA = 25°C, VFB = 0V 270 310 ns
START-UP
Soft start 1 2.5 4 ms
PGOOD
RatioOV Overvoltage protection 120%
RatioPG Relative power good level Low to high 72%
AUXILIARY LDOs
VPWR3,4_VIN Input voltage range LDO1 (PWR4), LDO2 (PWR3) 3.3 12 20 V
PGOOD Power good PWR3,4_VOUT PWR3,4_VOUT rising 80%
PWR3,4_VOUT falling 60%
OVP Overvoltage Protection PWR3,4_VOUT 7 V
DC output voltage accuracy PWR3,4_VOUT IOUT= 0mA –3% 3%
Regulator current limit(2) 300 340 400 mA
tON Turn-on time to 80% of VOUT = PWR3 and PWR4, C= 1µF 40 µs
LDO2 (PWR3)
VPWR3_VOUT Output Voltage PWR3_VOUT 2.5 V
Load Current capability 200 mA
DC Load regulation PWR3_VOUT VOUT= 2.5V, IOUT= 5 to 200mA –70 mV/A
DC Line regulation PWR3_VOUT VOUT= 2.5V, IOUT= 5mA, PWR3_VIN = 3.3 to 20V 30 µV/V
LDO1 (PWR4)
VPWR4_VOUT Output Voltage PWR4_VOUT 3.3 V
Load Current capability 200 mA
DC Load regulation PWR4_VOUT VOUT= 3.3V, IOUT= 5 to 200mA –70 mV/A
DC Line regulation PWR4_VOUT VOUT= 3.3V, IOUT= 5mA, PWR4_VIN= 4 to 20V 30 µV/V
Regulator dropout At 25mA, VOUT= 3.3V, VPWR4_VIN= 3.3V 48 mV
MEASUREMENT SYSTEM
LABB
τRC Settling time To 1% of final value(2). 4.6 6.6 µs
To 0.1% of final value(2) 7 10
VACMPR_IN_LABB Input voltage range ACMPR_IN_LABB 0 1.5 V
Sampling window ACMPR_IN_LABB Programmable per 7µs 7 28 µs
DIGITAL CONTROL — LOGIC LEVELS AND TIMING CHARACTERISTICS
VSPI_VIN SPI supply voltage range SPI_VIN 1.7 3.6 V
VOL Output low-level RESET_Z, ACMPR_OUT, CLK_OUT. IO = 0.3mA sink current 0 0.3 V
SPI_DOUT. IO = 5mA sink current 0 0.3 × VSPI_VIN
INT_Z. IO = 1.5mA sink current 0 0.3 × VSPI_VIN
VOH Output high-level RESET_Z, ACMPR_OUT, CLK_OUT. IO = 0.3mA source current 1.3 2.5 V
SPI_DOUT. IO = 5mA source current 0.7 × VSPI_VIN VSPI_VIN
VIL Input low-level PROJ_ON, CH_SEL0, CH_SEL1 0 0.4 V
SPI_CSZ, SPI_CLK, SPI_DIN 0 0.3 × VSPI_VIN
VIH Input high-level PROJ_ON, CH_SEL0, CH_SEL1 1.2 V
SPI_CSZ, SPI_CLK, SPI_DIN 0.7 × VSPI_VIN VSPI_VIN
IBIAS Input bias current VIO= 3.3V, any digital input pin 0.1 µA
SPI_CLK SPI clock frequency(4) Normal SPI mode, DIG_SPI_FAST_SEL = 0, ƒOSC = 9MHz 0 36 MHz
Fast SPI mode, DIG_SPI_FAST_SEL = 1, VSPI_VIN> 2.3V, ƒOSC = 9MHz 20 40
tDEGLITCH Deglitch time CH_SEL0, CH_SEL1(2). 300 ns
INTERNAL OSCILLATOR
ƒOSC Oscillator frequency 9 MHz
Frequency accuracy TA= 0 to 70°C –5% 5%
THERMAL SHUTDOWN
TWARN Thermal warning (HOT threshold) 120 °C
Hysteresis 10
TSHTDWN Thermal shutdown (TSD threshold) 150 °C
Hysteresis 15
(1) Including rectifying diode
(2) Not production tested
(3) Take care to not exceed the max power dissipation. Refer to Thermal Considerations.
(4) Maximum depends linearly on oscillator frequency fOSC.
(5) Take care that the capacitor has the specified capacitance at the related voltage, that is VOFFSET, VBIAS, or VRESET.
(6) VIN must be higher than the UVLO voltage setting, including after accounting for AC noise on VIN, for the DLPA3082 to fully operate. While 6.0V is the minimum VIN voltage supported, TI recommends that the UVLO is never set below 6.21V for a fault fast power down. 6.21V gives a margin above 6.0V to protect against the case where someone suddenly removes the VIN’s power supply which causes the VIN voltage to drop rapidly. Failure to keep VIN above 6.0V before the mirrors are parked and VOFS, VRST, and VBIAS supplies are properly shut down results in permanent damage to the DMD. Since 6.21V is .21V above 6.0V, when UVLO trips there is time for the DLPA3082 and DLPC84xx to park the DMD mirrors and do a fast shutdown of supplies VOFS, VRST, and VBIAS. For whatever UVLO setting is used, if VIN’s power supply is suddenly removed enough bulk capacitance can be included on VIN inside the projector to keep VIN above 6.0V for at least 100μs after UVLO trips.
(7) UVLO cannot be used for normal power down operation, it is meant as a protection from power loss.
(8) General purpose buck2 (PWR6) is currently supported.