DLPU133B March   2024  – August 2026 DLPC964

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Description
  6. 3 Get Started
  7. 4 Features
  8. 5 Evaluation Module Overview
    1. 5.1 Kit Contents
    2. 5.2 Specification
    3. 5.3 Assumptions
    4. 5.4 Apps FPGA Hardware Target
  9. 6 Apps FPGA Modules
    1. 6.1  Apps FPGA Block Diagram
    2. 6.2  BPG Module
    3. 6.3  BRG Module
      1. 6.3.1 Start Signal Logic
      2. 6.3.2 Delay Needed Logic
      3. 6.3.3 Blocks Sent and Loaded Logic
    4. 6.4  BRG_ST Module
    5. 6.5  PGEN Module
    6. 6.6  PGEN_MCTRL Module
    7. 6.7  PGEN_SCTRL Module
    8. 6.8  PGEN_PRM Module
    9. 6.9  PGEN_ADDR_ROM
    10. 6.10 HSSTOP Module
    11. 6.11 SSF Module
    12. 6.12 ENC Module
    13. 6.13 Xilinx IP
      1. 6.13.1 PGEN_SPBROM_v3
      2. 6.13.2 MAINPLL
      3. 6.13.3 AURORA_APPS_TX_X3LN_CLOCK_MODULE
      4. 6.13.4 AURORA_APPS_TX_X3LN_CHANNEL_WRAPPER
    14. 6.14 Reference Documents
    15. 6.15 DLPC964 Apps FPGA IO
    16. 6.16 Key Definitions
  10. 7 Functional Configuration
    1. 7.1 Blocks Enabled
    2. 7.2 Pattern Cycle Enable
      1. 7.2.1 North/South Flip
      2. 7.2.2 TPG Patterns
      3. 7.2.3 Pattern Mode
      4. 7.2.4 Switching Modes
      5. 7.2.5 Changing the BPG Patterns
  11. 8 Appendix
    1. 8.1 Vivado Chipscope Captures
    2. 8.2 DLPC964 Apps Bitstream Loading
      1. 8.2.1 Loading Bitstream onto FPGA
      2. 8.2.2 Loading Bitstream onto Flash
    3. 8.3 Interfacing To DLPC964 Controller with Aurora 64B/66B
      1. 8.3.1 Theory of Operation
      2. 8.3.2 Overview
      3. 8.3.3 Aurora 64B/66B TX Core and RTL Generation
        1. 8.3.3.1  Select Aurora 64B66B From IP Catalog
        2. 8.3.3.2  Configure Core Options
        3. 8.3.3.3  Lane Configurations
        4. 8.3.3.4  Shared Logic Options
        5. 8.3.3.5  Generate Example Design Files
        6. 8.3.3.6  RTL File List
        7. 8.3.3.7  Single Channel 3-Lane Aurora Core RTL Wrapper
        8. 8.3.3.8  Four Channels 12 Lanes Top Level RTL Wrapper
        9. 8.3.3.9  Block Start with Block Control Word
        10. 8.3.3.10 Block Complete with DMDLOAD_REQ
        11. 8.3.3.11 DMDLOAD_REQ Setup Time Requirement
        12. 8.3.3.12 Single Channel Transfer Mode
        13. 8.3.3.13 DMD Block Array Data Mapping
        14. 8.3.3.14 Xilinx IBERT
  12. 9 Additional Information
    1. 9.1 Abbreviations and Acronyms
  13. 10Related Documentation from Texas Instruments
  14. 11Revision History

6.9 PGEN_ADDR_ROM

Because a single line is the smallest loadable part of the DMD, the user specifies the number of lines desired to be loaded. However, the Aurora GTH channel is 192 bits wide, so the PGEN_ADDR_ROM translates the number of lines to be loaded into a ROM address using the following formula:

MAX_ROM_ADDRESS = (# of lines) × 5 + CEIL(# of lines / 3)