Design Goals

Design Description

A power-supply margining circuit is used for tuning the output of a power converter. This is done either to adjust the offset and drift of the power-supply output or to program a desired value at the output. Adjustable power supplies like LDOs and DC/DC converters provide a feedback or adjust input that is used to set the desired output. A precision voltage output DAC is designed for controlling the power-supply output linearly. An example power-supply margining circuit is shown in the following figure. Typical applications of power-supply margining are in test and measurement, communications equipment, and general purpose power supply modules.

Design Notes

1. Choose a DAC with required resolution, pulldown resistor value, and output range
2. Derive the relationship of the DAC output to V_OUT
3. Choose R₁ based on typical current through the feedback circuit
4. Calculate the start-up or nominal value of V_DAC, considering the power-down and power-up conditions of the DAC
5. Select R₂, and R₃ such that the desired start-up output voltage is met along with the DAC output voltage range for the desired tuning range
6. Calculate the margin low and margin high DAC outputs
7. Choose a compensation capacitor to get the desired step response

Design Steps

1. Select the switching DC/DC converter TPS5450 for the calculations. The DAC53608 device is an ultra-low cost, 10-bit, 8-channel unipolar output DAC designed for such applications
2. The output voltage of the power supply is given by
   

   where

   • I₁ is the current flowing through R₁
   • I₂ is the current flowing through R₂
   • I₃ is the current flowing through R₃

   DACs in this application typically include power-down mode, which includes an internal pulldown resistor at the voltage output. Hence, replacing the values of the currents in the previous equation yields:

   • When DAC is in power-down mode:
     
   • When DAC output is powered-up:
     

   For DAC53608, R_PULLDOWN is 10kΩ. For the LDO device TPS5450, the value of V_REF is 1.221V.

3. R₁ can be calculated with the following method:
   The current through the FB pin of the TPS5450 device is negligible. Select I₁ to be 50µA. So, R₁ is calculated as follows:
   

   The nominal value of I₁ is given by:

   • When DAC is in power-down mode:
     
   • When DAC output is powered-up:
     

   The values of I₁ at margin high and margin low outputs are given by:

   
   
   
4. The nominal, or start-up value of V_DAC is calculated by the following method:

   To make sure the 10-kΩ resistor does not impact when the DAC is transitioning from power-down to power-up, the power-up value for the DAC voltage is calculated with:

   

   The previous equation is further simplified to:

   
5. The values of R₂ and R₃ are calculated as follows:

   If the power-up or nominal value of V_DAC is kept at 1/3 of V_REF, that is, 407mV, then R₃ is 2 × 10kΩ = 20kΩ. And, R₂ can be calculated as:

   

   Replacing the value of R₃, calculate R₂ = 131.3kΩ.

6. Subtracting the margin high and nominal values of I₁ and the corresponding equations yields:
   

   The margin high value of V_DAC is 275mV and similarly, the margin low value is calculated as 539mV using the following equation:

   
7. The step response of this circuit without a compensation capacitor causes the inductor current to reach its limit as shown in the following figure. This kind of surge can take the inductor into saturation. To minimize the surge, a compensation capacitor C₁ is used as the circuit diagram shows. The value of this capacitance is usually obtained through simulation. A comparative output shows the waveforms with a compensation capacitor of 10nF.

Design Featured Devices and Alternative Parts

Link to Key Files

Texas Instruments, SBAM416 source files, support software