SBAA483 February   2021 ADS1120 , ADS112C04 , ADS112U04 , ADS114S06 , ADS114S06B , ADS114S08 , ADS114S08B , ADS1220 , ADS122C04 , ADS122U04 , ADS124S06 , ADS124S08 , ADS125H02 , ADS1260 , ADS1261 , ADS1262 , ADS1263

 

  1.   Abstract
  2.   Trademarks
  3. 1Introduction
  4. 2Features Used to Detect Wire Breaks in RTD Systems
    1. 2.1 Detecting a Wire Break Using a Continuous VREF Monitor
    2. 2.2 Detecting a Wire Break Using a Periodic VREF Monitor
    3. 2.3 Detecting a Wire Break Using Separate Analog Inputs
  5. 3Wire-Break Detection Methods for Different RTD Configurations
    1. 3.1 Wire-Break Detection Using 2-Wire RTDs
    2. 3.2 Wire-Break Detection Using 3-Wire RTDs
      1. 3.2.1 Wire-Break Detection in a One-IDAC, 3-Wire RTD System
        1. 3.2.1.1 Detecting a Break in Lead 2 in a One-IDAC, 3-Wire RTD System
          1. 3.2.1.1.1 Detecting a Break in Lead 2 in a One-IDAC, 3-Wire RTD System Using a High-Side RREF
        2. 3.2.1.2 Wire-Break Detection Summary for a One-IDAC, 3-Wire RTD System
      2. 3.2.2 Wire-Break Detection in a Two-IDAC, 3-Wire RTD System
        1. 3.2.2.1 Detecting Lead 1 or 2 breaks in a two IDAC, 3-wire RTD system using a low-side RREF
        2. 3.2.2.2 Detecting Lead 1 or 2 Breaks in a Two-IDAC, 3-Wire RTD System Using a High-Side RREF
        3. 3.2.2.3 Wire-Break Detection Summary for a Two-IDAC, 3-Wire RTD System
    3. 3.3 Wire-Break Detection in a 4-Wire RTD System
      1. 3.3.1 Detecting Lead 2 and Lead 3 Breaks in a 4-Wire RTD System Using a Low-Side RREF
      2. 3.3.2 Detecting Lead 2 and Lead 3 Breaks in a 4-Wire RTD System Using a High-Side RREF
      3. 3.3.3 Wire-Break Detection Summary for a 4-Wire RTD System
  6. 4Settling Time Considerations for RTD Wire-Break Detection
  7. 5Summary
  8.   A How Integrated PGA Rail Detection Helps Identify Wire Breaks
  9.   B Pseudo-Code for RTD Wire-Break Detection
    1.     B.1 Pseudo-Code for a 2-Wire RTD System (Low-Side or High-Side RREF)
    2.     B.2 Pseudo-Code for a One-IDAC, 3-Wire RTD System (Low-Side or High-Side RREF)
    3.     B.3 Pseudo-Code for a Two-IDAC, 3-Wire RTD System (Low-Side or High-Side RREF)
    4.     B.4 Pseudo-Code for a 4-Wire RTD System (Low-Side or High-Side RREF)

3.2.2.2 Detecting Lead 1 or 2 Breaks in a Two-IDAC, 3-Wire RTD System Using a High-Side RREF

In the high-side RREF configuration, only one IDAC current flows through RREF under normal operating conditions, leading to distinct fault detection schemes depending on which lead breaks. Figure 3-9 shows how the current flows differently if lead 1 breaks (left) versus lead 2 (right).

GUID-20210107-CA0I-GSJJ-WLM3-QSXM9ZQ2NMGW-low.gif Figure 3-9 Lead 1 (Left) or Lead 2 (Right) Breaks in a Two-IDAC, 3-Wire RTD System Using a High-Side RREF

As shown in Figure 3-9a, the VREF monitor detects a break in lead 1 in the high-side RREF configuration. The VREF monitor is tripped in this case because the break in lead 1 eliminates the path to ground for IDAC1 such that there is a near-zero voltage across RREF. The current from IDAC2 still flows through RBIAS to ground, but does not impact the result observed by the VREF monitor.

A break in lead 2 is not detectable by the VREF monitor in the high-side RREF configuration. As Figure 3-9b shows, the IDAC1 current still flows through RREF such that the VREF monitor does not indicate a fault. Instead, use a change in the measurement result to detect a break in lead 2.

Under normal conditions in a two-IDAC, 3-wire RTD system using a high-side RREF, expect the following voltages (given by Equation 8 and Equation 9) at the AINx pins:

Equation 8. VAINP (no wire break) = IDAC1 · (RRTD + RLEAD1 + RLEAD3 + RBIAS) + IDAC2 · (RLEAD3 + RBIAS)
Equation 9. VAINN (no wire break) = IDAC1 · (RLEAD3 + RBIAS) + IDAC2 · (RLEAD2 + RLEAD3 + RBIAS)

The resulting differential voltage, VIN (no wire break), between AINP and AINN is given by Equation 10, assuming RLEAD1 = RLEAD2 = RLEAD3 and IDAC1 = IDAC2:

Equation 10. VIN (no wire break) = VAINP – VAINN = IDAC1 · RRTD

Therefore, without a fault to alter the circuit operation, the voltage at AINP is always greater than AINN because the IDAC current only flows in one direction. As a result, normal operating conditions always yield a positive output code.

Comparatively, a break in lead 2 eliminates the path to ground for IDAC2, forcing the IDAC2 current into the high-impedance analog input, AINN. The high impedance acts as an open circuit, raising the voltage level on AINN as the IDAC circuitry tries to maintain constant current. Eventually, this voltage is driven to the positive supply (AVDD) such that AINN is now approximately at AVDD as well.

Moreover, the voltage at AINP has actually reduced because IDAC2 is no longer able to flow through RLEAD3 and RBIAS, resulting in an absolute voltage at AINP given by Equation 11:

Equation 11. VAINP(wire break) = IDAC1 · (RRTD + RLEAD1 + RLEAD3 + RBIAS)

If AINN is pulled to AVDD and AINP is reduced in magnitude, VAINN (wire break) is greater than VAINP (wire break), resulting in a negative output code.

This diagnostic routine is very similar to the one employed in Section 3.2.1.1.1 for the one-IDAC, 3-wire RTD system using a high-side RREF, though in this case there is no need to switch to the ADC internal reference or change the IDAC current magnitude. In fact, neither detection scheme in the two-IDAC, 3-wire RTD system using a high-side RREF actually requires a separate diagnostic measurement, allowing wire-break detection to occur without interrupting the precision RTD measurement.