1 Introduction

Each channel of the TLV320ADCx120 and PCMx120-Q1 devices follows the signal chain shown in Figure 1-1. In this signal chain, each channel supports an analog differential or single-ended signal or a digital pulse density modulation (PDM) digital microphone. In TLV320ADCx120 and PCMx120-Q1 device families, the analog input signal is amplified by a Programmable Gain Amplifier (PGA) and then converted by a high-performance ADC into a digital signal. The PGA gains the input signal to match the full scale of the ADC. The digital signal has a programmable phase calibration to adjust the phase delay of each channel in steps of one modulator clock cycle. This allows the system to match the phase across different channels. The phase-calibrated digital signal is then decimated through a set of linear phase filters or low-latency filters. DC offset is removed from the decimated signal through a Digital High-Pass Filter (HPF) with three preset cutoff frequencies or a fully programmable cutoff frequency. Note that DC shifts are caused by mismatches in common-mode voltages. The output of the HPF is gain calibrated with 0.1-dB steps and summed with other channels. The gain calibration matches the gain across different channels, particularly if the channels have microphones with varying gain values. The output is then filtered by the Digital Biquad Filters and gained by the volume control.

Figure 1-1 TLV320ADCx120 and PCMx120-Q1 Channel Signal Chain Processing Flow Chart

This application note concentrates on how to configure the Digital Biquad Filters. The Digital Biquad Filters are digitally implemented as a set of IIR filters.