2 Target Mode Power Consumption With PLL Disabled

This section describes the typical current consumption of the TAD52xx devices, when the PLL is disabled with AVDD set to 1.8V and 3.3V.

The PLL is disabled by:

1. Setting the corresponding B0_P0_R52[7] (PLL_DIS) and (DAC_LOW_PWR_FILT) bit fields.
2. Enabling the B0_P0_R79[2] field.

By default, the bit clock is used as the clock source to the internal block when the PLL is disabled. Alternatively, an external clock source (CCLK) can be used in the device through one of the GPI capable pins (GPIOx or GPIx), if the system has a low jitter clock available.

• If GPIOx is used for the CCLK input, the appropriate GPIOx_CFG bit field in the GPIOx_CFG0 register must be configured for GPI function.
• If GPIx is used for the CCLK input, the appropriate GPIx_CFG bit field in the GPI_CFG register must be enabled for GPI function.
• The pin configured for GPI must be configured as CCLK, this configuration is done by configuring B0_P0_R15[6:5] (CCLK_SEL), based on the pin configured.
• With the CCLK configured, the external CCLK must be used as the clock source, this configuration is done by configuring B0_P0_R52[3:1] (CLK_SRC_SEL).
• The CCLK must be synchronized with the frame syn. For example, the CCLK frequency must be an integer multiple of the frame sync frequency.
• Once configured, the device runs on the external CCLK as the clock source.

In Table 2-1, the power consumption measurements have the biquad filters disabled, and the idle DAC output (or outputs) and an external CCLK of 12.288MHz are provided as the clock source to the device through the GPIO1 pin.