SBAA608 August   2025 TAD5112 , TAD5112-Q1 , TAD5142 , TAD5212 , TAD5212-Q1 , TAD5242

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Target Mode Power Consumption With PLL Disabled
  6. 3Target Mode Power Consumption With PLL Enabled
  7. 4Settings for Lowest Power Consumption
  8. 5Summary
  9. 6References

1 Introduction

Power consumption on TAD52xx devices is highly dependent on the enabled features and usage scenarios. The following tables summarize the power consumption across:

  • Supply voltage
  • Sampling frequency
  • Enabled channel count
  • Decimation filter
  • Bit clock to frame sync ratio
  • PLL state (enabled or disabled)
  • Output loads
  • Converted word length

The following tables report the average idle-channel current consumed on the analog supply (AVDD). This supply includes all the internal analog and digital circuits but excludes the current consumed by the I/O (input/output) pins due to application dependencies. I/O power is dependent upon:

  • Load capacitance of the system bus interface
  • Data input clock rate
  • Bus interface pullups or pulldowns
  • Frequency of I2C commands sent by the host