SBAA608 August   2025 TAD5112 , TAD5112-Q1 , TAD5142 , TAD5212 , TAD5212-Q1 , TAD5242

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1Introduction
  5. 2Target Mode Power Consumption With PLL Disabled
  6. 3Target Mode Power Consumption With PLL Enabled
  7. 4Settings for Lowest Power Consumption
  8. 5Summary
  9. 6References

4 Settings for Lowest Power Consumption

To minimize the power consumption of the TAD52xx devices, verify that unused modules are disabled, use the lowest sampling rate, bit clock, and controller clock required by the application, and operate at the lowest AVDD and IOVDD supply voltage possible. The following list summarizes the settings and registers for lowest power operation:

  • Operate at the lowest supply voltage possible. AVDD and IOVDD support a 1.8V or 3.3V supply, independently (AVDD and IOVDD can have different supply levels).
    • Unused digital inputs, tie to digital ground.
    • Unused outputs, leave unconnected.
  • Disable unused DAC channels through the BO_PO_R118 (IN_CH_EN) register.
  • Disable MICBIAS power, if unused, through the BO_PO_R120 (PWR_CFG) register.
  • Operate at the lowest sample rate possible.
  • Disable PLL, if the system supplies a low jitter controller clock. Refer to Section 2 for a description of the settings to disable PLL.
  • Disable unused post-processing blocks:
    • Disable biquad filters, if unused, through the BO_PO_R115[4:3] (DSP_CFG) register.
  • Select ultra-low latency over linear phase decimation filters (if the application allows) through the BO_PO_R115[7:6] (DSP_CFG) register.
  • Use the smallest word length permissible by the application through the BO_PO_R26[5:4] (PASI_WLEN) register for primary ASI and BO_P3_R26[5:4] (SASI_WLEN) in cases of secondary ASI.