Beyond the capacitance value itself, the parasitic impedances of the output capacitor play a critical role — particularly at the moment the transient begins. The ESR introduces an immediate resistive voltage step: $\Delta V_{ESR} \approx \Delta I_{LOAD}\times ESR$

The ESL adds a further inductive spike during fast current transitions: $\Delta V_{ESL}=ESL\times \left(\raisebox{1ex}{$d\Delta I_{LOAD}$}\!\left/ \!\raisebox{-1ex}{$dt$}\right.\right)$

In applications with high load current slew rates, ESL can in fact dominate the initial voltage spike, making capacitor selection about more than just capacitance value. Low-ESR, low-ESL ceramic capacitors (MLCCs) are generally preferred. Where higher bulk capacitance is needed, a combination of MLCCs and bulk capacitors is commonly used, placing the MLCCs physically closest to the load to minimize parasitic inductance in the current path.