Before the control loop reacts, the output capacitor alone is responsible for supplying or absorbing the sudden change in load current. During this phase, the initial peak voltage deviation (ΔV) is determined entirely by the output capacitor's value and its parasitic impedances, primarily the equivalent series resistance (ESR) and equivalent series inductance (ESL). A larger output capacitance with lower parasitics will limit the initial voltage deviation, buying time for the control loop to respond.