SBAS535D August 2013 – June 2026 ADS1120
PRODUCTION DATA
At gains of 1, 2, and 4, set the PGA_BYPASS bit in the configuration register to disable and bypass the low-noise PGA. Disabling the PGA lowers the overall power consumption and also removes the restrictions of Equation 12 through Equation 14 for the common-mode input voltage range, VCM. The usable absolute and common-mode input voltage range is (AVSS – 0.1V ≤ VAINx, VCM ≤ AVDD + 0.1V) when the PGA is disabled.
To measure single-ended signals that are referenced to AVSS (AINP = VIN, AINN = AVSS), the PGA must be bypassed. Configure the device for single-ended measurements by either connecting one of the analog inputs to AVSS externally or by using the internal AVSS connection of the multiplexer (MUX[3:0] settings 1000b through 1011b). When configuring the internal multiplexer for settings where AINN = AVSS (MUX[3:0] = 1000b through 1011b) the PGA is automatically bypassed and disabled irrespective of the PGA_BYPASS setting and gain is limited to 1, 2, and 4. The PGA is always enabled for gain settings greater than 4, regardless of the PGA_BYPASS setting.
When the PGA is disabled, the device uses a buffered switched-capacitor stage to obtain gains 1, 2, and 4. An internal buffer in front of the switched-capacitor stage ensures that the effect on the input loading resulting from the capacitor charging and discharging is minimal. See Figure 6-21 to Figure 6-26 for the typical values of absolute input currents (current flowing into or out of each input) and differential input currents (difference in absolute current between positive and negative input) when the PGA is disabled.
For signal sources with high output impedance, external buffering can still be necessary. Active buffers introduce noise and also introduce offset and gain errors. Consider all of these factors in high-accuracy applications.