SBAS535D August   2013  – June 2026 ADS1120

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 SPI Timing Requirements
    7. 6.7 SPI Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
    1. 7.1 Noise Performance
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Multiplexer
      2. 8.3.2  Low-Noise PGA
        1. 8.3.2.1 PGA Common-Mode Voltage Requirements
        2. 8.3.2.2 Bypassing the PGA
      3. 8.3.3  Voltage Reference
      4. 8.3.4  Clock Source
      5. 8.3.5  Modulator
      6. 8.3.6  Digital Filter
      7. 8.3.7  Output Data Rate
      8. 8.3.8  Excitation Current Sources
      9. 8.3.9  Low-Side Power Switch
      10. 8.3.10 Sensor Detection
      11. 8.3.11 System Monitor
      12. 8.3.12 Offset Calibration
      13. 8.3.13 Temperature Sensor
        1. 8.3.13.1 Converting From Digital Codes to Temperature
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Up and Reset
      2. 8.4.2 Conversion Modes
        1. 8.4.2.1 Single-Shot Conversion Mode
        2. 8.4.2.2 Continuous Conversion Mode
      3. 8.4.3 Operating Modes
        1. 8.4.3.1 Normal Mode
        2. 8.4.3.2 Duty-Cycle Mode
        3. 8.4.3.3 Turbo Mode
        4. 8.4.3.4 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Chip Select (CS)
        2. 8.5.1.2 Serial Clock (SCLK)
        3. 8.5.1.3 Data Ready (DRDY)
        4. 8.5.1.4 Data Input (DIN)
        5. 8.5.1.5 Data Output and Data Ready (DOUT/DRDY)
        6. 8.5.1.6 SPI Timeout
      2. 8.5.2 Data Format
      3. 8.5.3 Commands
        1. 8.5.3.1 RESET (0000 011xb)
        2. 8.5.3.2 START/SYNC (0000 100xb)
        3. 8.5.3.3 POWERDOWN (0000 001xb)
        4. 8.5.3.4 RDATA (0001 xxxxb)
        5. 8.5.3.5 RREG (0010 rrnnb)
        6. 8.5.3.6 WREG (0100 rrnnb)
      4. 8.5.4 Reading Data
      5. 8.5.5 Sending Commands
      6. 8.5.6 Interfacing with Multiple Devices
    6. 8.6 Register Map
      1. 8.6.1 Configuration Registers
      2. 8.6.2 Register Descriptions
        1. 8.6.2.1 Configuration Register 0 (Address = 00h) [reset = 00h]
        2. 8.6.2.2 Configuration Register 1 (Address = 01h) [reset = 00h]
        3. 8.6.2.3 Configuration Register 2 (Address = 02h) [reset = 00h]
        4. 8.6.2.4 Configuration Register 3 (Address = 03h) [reset = 00h]
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Serial Interface Connections
      2. 9.1.2 Analog Input Filtering
      3. 9.1.3 External Reference and Ratiometric Measurements
      4. 9.1.4 Establishing a Proper Common-Mode Input Voltage
      5. 9.1.5 Unused Inputs and Outputs
      6. 9.1.6 Pseudo Code Example
    2. 9.2 Typical Applications
      1. 9.2.1 K-Type Thermocouple Measurement (–200°C to +1250°C)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 3-Wire RTD Measurement (–200°C to +850°C)
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Design Variations for 2-Wire and 4-Wire RTD Measurements
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Resistive Bridge Measurement
        1. 9.2.3.1 Design Requirements
        2. 9.2.3.2 Detailed Design Procedure
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-Supply Sequencing
      2. 9.3.2 Power-Supply Ramp Rate
      3. 9.3.3 Power-Supply Decoupling
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

8.6.2.1 Configuration Register 0 (Address = 00h) [reset = 00h]

Figure 8-32 Configuration Register 0
7 6 5 4 3 2 1 0
MUX[3:0] GAIN[2:0] PGA_BYPASS
R/W-0000b R/W-000b R/W-0b
Table 8-10 Configuration Register 0 Field Descriptions
Bit Field Type Reset Description
7:4 MUX[3:0] R/W 0000b Input multiplexer configuration
These bits configure the input multiplexer.
For settings where AINN = AVSS, the PGA must be disabled (PGA_BYPASS = 1) and only gains 1, 2, and 4 can be used.


0000b : AINP = AIN0, AINN = AIN1
0001b : AINP = AIN0, AINN = AIN2
0010b : AINP = AIN0, AINN = AIN3
0011b : AINP = AIN1, AINN = AIN2
0100b : AINP = AIN1, AINN = AIN3
0101b : AINP = AIN2, AINN = AIN3
0110b : AINP = AIN1, AINN = AIN0
0111b : AINP = AIN3, AINN = AIN2
1000b : AINP = AIN0, AINN = AVSS
1001b : AINP = AIN1, AINN = AVSS
1010b : AINP = AIN2, AINN = AVSS
1011b : AINP = AIN3, AINN = AVSS
1100b : (VREFPx – VREFNx) / 4 monitor (PGA bypassed)
1101b : (AVDD – AVSS) / 4 monitor (PGA bypassed)
1110b : AINP and AINN shorted to (AVDD + AVSS) / 2
1111b : Reserved
3:1 GAIN[2:0] R/W 000b Gain configuration
These bits configure the device gain.
Gains 1, 2, and 4 can be used without the PGA. In this case, gain is obtained by a switched-capacitor structure.


000b : Gain = 1
001b : Gain = 2
010b : Gain = 4
011b : Gain = 8
100b : Gain = 16
101b : Gain = 32
110b : Gain = 64
111b : Gain = 128
0 PGA_BYPASS R/W 0b Disables and bypasses the internal low-noise PGA
Disabling the PGA reduces overall power consumption and allows the common-mode voltage range (VCM) to span from AVSS – 0.1V to AVDD + 0.1V.
The PGA can only be disabled for gains 1, 2, and 4.
The PGA is always enabled for gain settings 8 to 128, regardless of the PGA_BYPASS setting.


0b : PGA enabled
1b : PGA disabled and bypassed