SBAS883A February 2018 – June 2018 OPT3101
PRODUCTION DATA.
| 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
| RESERVED | 0 | I2C_RW | I2C_EN | I2C_TRIG_REG | FRAME_VD_TRIG | RESERVED | |
| R/W - 0h | R/W - 0h | R/W - 1h | R/W - 0h | R/W - 0h | R/W - 1h | R/W - 0h | |
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
| RESERVED | ADDR_SLAVE_EEPROM | ||||||
| R/W - 0h | R/W - 1h | ||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ADDR_SLAVE_EEPROM | SWAP_READ_DATA | RESERVED | |||||
| R/W - 10h | R/W - 0h | R/W - 0h | |||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 23 | RESERVED | R/W | 0h | Always read or write 0h. |
| 21:20 | I2C_RW | R/W | 1h | Chooses R/W for I2C host operation.
0: Write | 1: Read LSB: first transaction, MSB: second transaction |
| 19 | I2C_EN | R/W | 0h | Enables the I2C host. |
| 18 | I2C_TRIG_REG | R/W | 0h | The trigger register for I2C transactions |
| 17 | FRAME_VD_TRIG | R/W | 1h | When this bit is 1, the I2C host is triggered on every sample start. Else it is triggered based on the setting of I2C_TRIG_REG. |
| 16:9 | RESERVED | R/W | 0h | Always read or write 0h. |
| 8:2 | ADDR_SLAVE_EEPROM | R/W | 50h | External EEPROM I2C slave address. |
| 1 | SWAP_READ_DATA | R/W | 0h | Setting this bit to 1 reverses the data read by I2C host from [7:0] to [0:7]. |
| 0 | RESERVED | R/W | 0h | Always read or write 0h. |