SBASAS7A August   2024  – June 2025 AMC0106M05

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information (DEN Package)
    5. 5.5 Package Characteristics
    6. 5.6 Electrical Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Input
      2. 6.3.2 Modulator
      3. 6.3.3 Isolation Channel Signal Transmission
      4. 6.3.4 Digital Output
        1. 6.3.4.1 Output Behavior in Case of a Full-Scale Input
        2. 6.3.4.2 Output Behavior in Case of a Missing High-Side Supply
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Shunt Resistor Sizing
        2. 7.2.2.2 Input Filter Design
        3. 7.2.2.3 Bitstream Filtering
        4. 7.2.2.4 Designing the Bootstrap Supply
      3. 7.2.3 Application Curve
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.6 Electrical Characteristics

minimum and maximum specifications are at TA = –40°C to 125°C, AVDD = 3.0V to 5.5V, DVDD = 2.7V to 5.5V, VINP = –50mV to 50mV, VINN = 0V, and sinc3 filter with OSR = 256 (unless otherwise noted); typical specifications are at TA = 25°C, CLKIN = 20MHz with 50% duty cycle, AVDD = 5V, and DVDD = 3.3V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
CIN Effective input sampling capacitance  8 pF
RIN Input impedance  fCLK = 10MHz 10.5 12.5 14.5 kΩ
fCLK = 20MHz 5.3 6.3 7.3
IINP Input current  VIN = (VINP – VINN) = VFSR, MAX,
fCLK = 10MHz		 4 μA
VIN = (VINP – VINN) = VFSR, MAX,
fCLK = 20MHz		 8
IINN Input current  VIN = (VINP – VINN) = VFSR, MAX,
fCLK = 10MHz		 –4 μA
VIN = (VINP – VINN) = VFSR, MAX,
fCLK = 20MHz		 –8
CMTI Common-mode transient immunity  150 kV/μs
DC ACCURACY 
EO Offset error 
INP = INN = AGND, TA = 25°C		 –200 10 200 µV
TCEO Offset error temperature drift(3) –1.2 1.2 µV/°C
EG Gain error(1)  TA = 25°C –0.3% ±0.04% 0.3%
TCEG Gain error temperature drift(4) –50 ±20 50 ppm/°C
INL Integral nonlinearity(2) Resolution: 16 bits –6 ±1 6 LSB
DNL Differential nonlinearity  Resolution: 16 bits –0.99 0.99 LSB
CMRR Common-mode rejection ratio  INP = INN, fIN = 0Hz,
VCM min ≤ VIN ≤ VCM max		 –99 dB
INP = INN, fIN from 0.1Hz to 10kHz,
VCM min ≤ VIN ≤ VCM max		 –100
PSRR Power-supply rejection ratio  AVDD DC PSRR, INP = INN = AGND,
AVDD from 3.0V to 5.5V		 –100 dB
AVDD AC PSRR, INP = INN = AGND,
AVDD with 10-kHz / 100-mV ripple		 –100
AC ACCURACY 
SNR Signal-to-noise ratio  fIN = 1 kHz 84 dB
SINAD Signal-to-noise + distortion  fIN = 1 kHz 84 dB
THD Total harmonic distortion(5) 3.0V ≤ AVDD ≤ 5.5V, fIN = 1kHz,
5MHz ≤ fCLKIN ≤ 21MHz		 –103 dB
DIGITAL INPUT (CMOS Logic With Schmitt-Trigger)
IIN Input current DGND ≤ VIN ≤ DVDD 0 7 μA
CIN Input capacitance 4 pF
VIH High-level input voltage 0.7 × DVDD DVDD + 0.3 V
VIL Low-level input voltage –0.3 0.3 × DVDD V
DIGITAL OUTPUT (CMOS)
CLOAD Output load capacitance 15 30 pF
VOH High-level output voltage IOH = –4mA DVDD – 0.4 V
VOL Low-level output voltage IOL = 4mA 0.4 V
POWER SUPPLY
IAVDD High-side supply current  6.2 8.0 mA
IDVDD Low-side supply current  CLOAD = 15 pF 4.5 7.0 mA
AVDDUV High-side undervoltage detection threshold AVDD rising 2.4 2.6 2.8 V
AVDD falling 1.9 2.05 2.2
DVDDUV Low-side undervoltage detection threshold DVDD rising 2.3 2.5 2.7 V
DVDD falling 1.9 2.05 2.2
(1) This parameter is input referred.
(2) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer
function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.
(3) Offset error temperature drift is calculated using the box method, as described by the following equation:
TCEO = (EO,MAX – EO,MIN) / TempRange where EO,MAX and EO,MIN refer to the maximum and minimum EO values measured within the temperature range (–40 to 125℃).
(4) Gain error temperature drift is calculated using the box method, as described by the following equation:
TCEG (ppm) = ((EG,MAX - EG,MIN) / TempRange) x 104 where EG,MAX and EG,MIN refer to the maximum and minimum EG values (in %) measured within the temperature range (–40 to 125℃).
(5) THD is the ratio of the rms sum of the amplitudes of first five higher harmonics to the amplitude of the fundamental.