SBASAW0A February   2024  – November 2025 ADS1288

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements: 1.65V ≤ IOVDD ≤ 1.95V and 2.7V ≤ IOVDD ≤ 3.6V
    7. 5.7 Switching Characteristics: 1.65V ≤ IOVDD ≤ 1.95V and 2.7V ≤ IOVDD ≤ 3.6V
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
      2. 7.3.2 PGA and Buffer
        1. 7.3.2.1 Programmable Gain Amplifier (PGA)
        2. 7.3.2.2 Buffer Operation (PGA Bypass)
      3. 7.3.3 Voltage Reference Input
      4. 7.3.4 IOVDD Power Supply
      5. 7.3.5 Modulator
        1. 7.3.5.1 Modulator Overdrive
      6. 7.3.6 Digital Filter
        1. 7.3.6.1 Sinc Filter Section
        2. 7.3.6.2 FIR Filter Section
        3. 7.3.6.3 Group Delay and Step Response
          1. 7.3.6.3.1 Linear Phase Response
          2. 7.3.6.3.2 Minimum Phase Response
        4. 7.3.6.4 HPF Stage
      7. 7.3.7 Clock Input
      8. 7.3.8 GPIO
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Down Mode
      2. 7.4.2 Reset
      3. 7.4.3 Synchronization
        1. 7.4.3.1 Pulse-Sync Mode
        2. 7.4.3.2 Continuous-Sync Mode
      4. 7.4.4 Sample Rate Converter
      5. 7.4.5 Offset and Gain Calibration
        1. 7.4.5.1 OFFSET Register
        2. 7.4.5.2 GAIN Register
        3. 7.4.5.3 Calibration Procedure
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. 7.5.1.1 Chip Select (CS)
        2. 7.5.1.2 Serial Clock (SCLK)
        3. 7.5.1.3 Data Input (DIN)
        4. 7.5.1.4 Data Output (DOUT)
        5. 7.5.1.5 Data Ready (DRDY)
      2. 7.5.2 Conversion Data Format
      3. 7.5.3 Commands
        1. 7.5.3.1  Single Byte Command
        2. 7.5.3.2  WAKEUP: Wake Command
        3. 7.5.3.3  STANDBY: Software Power-Down Command
        4. 7.5.3.4  SYNC: Synchronize Command
        5. 7.5.3.5  RESET: Reset Command
        6. 7.5.3.6  Read Data Direct
        7. 7.5.3.7  RDATA: Read Conversion Data Command
        8. 7.5.3.8  RREG: Read Register Command
        9. 7.5.3.9  WREG: Write Register Command
        10. 7.5.3.10 OFSCAL: Offset Calibration Command
        11. 7.5.3.11 GANCAL: Gain Calibration Command
  9. 8 Register Map
    1. 8.1 Register Descriptions
      1. 8.1.1 ID/SYNC: Device ID, SYNC Register (Address = 00h) [Reset = xxxx0010b]
      2. 8.1.2 CONFIG0: Configuration Register 0 (Address = 01h) [Reset = 92h]
      3. 8.1.3 CONFIG1: Configuration Register 1 (Address = 02h) [Reset = 10h]
      4. 8.1.4 HPF0, HPF1: High-Pass Filter Registers (Address = 03h, 04h) [Reset = 32h, 03h]
      5. 8.1.5 OFFSET0, OFFSET1, OFFSET2: Offset Calibration Registers (Address = 05h, 06h, 07h) [Reset = 00h, 00h, 00h]
      6. 8.1.6 GAIN0, GAIN1, GAIN2: Gain Calibration Registers (Address = 08h, 09h, 0Ah) [Reset = 00h, 00h, 40h]
      7. 8.1.7 GPIO: Digital Input/Output Register (Address = 0Bh) [Reset = 000xx000b]
      8. 8.1.8 SRC0, SRC1: Sample Rate Converter Registers (Address = 0Ch, 0Dh) [Reset = 00h, 80h]
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Analog Power Supplies
      2. 9.3.2 Digital Power Supply
      3. 9.3.3 Grounds
      4. 9.3.4 Thermal Pad
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

5.9 Typical Characteristics

at TA = 25°C, AVDD1 = 5V, AVSS = 0V, AVDD2 = 2.5V, IOVDD = 1.8V, fCLK = 4.096MHz, VREFP = 2.5V, VREFN = 0V, PGA gain = 1, RS = 0Ω, VCM = 2.5V, and fDATA = 500SPS (unless otherwise noted)

ADS1288 Shorted Input FFT
Buffer mode
Figure 5-9 Shorted Input FFT
ADS1288 Shorted Input FFT
PGA gain = 16
Figure 5-11 Shorted Input FFT
ADS1288 Full-Scale Input FFT
PGA gain = 16
 
Figure 5-13 Full-Scale Input FFT
ADS1288 Dynamic Range vs PGA Gain
 
Figure 5-15 Dynamic Range vs PGA Gain
ADS1288 Offset Drift Distribution
30 units
Figure 5-17 Offset Drift Distribution
ADS1288 Gain Error Distribution
30 units
Figure 5-19 Gain Error Distribution
ADS1288 Gain Drift Distribution
30 units
Figure 5-21 Gain Drift Distribution
ADS1288 THD vs PGA Gain
AVDD1 = 3.3V, fIN = 31.25Hz, VIN = –0.5dBFS
Figure 5-23 THD vs PGA Gain
ADS1288 THD vs Source Impedance
fIN = 31.25Hz, VIN = –0.5dBFS
Figure 5-25 THD vs Source Impedance
ADS1288 PGA Input Current vs Input Voltage
 
Figure 5-27 PGA Input Current vs Input Voltage
ADS1288 Reference Input Current vs Temperature
 
Figure 5-29 Reference Input Current vs Temperature
ADS1288 CMRR vs Common-Mode Input Frequency
 
Figure 5-31 CMRR vs Common-Mode Input Frequency
ADS1288 Power-Supply Current vs Temperature
 
Figure 5-33 Power-Supply Current vs Temperature
ADS1288 IOVDD Current vs Data Rate
 
Figure 5-35 IOVDD Current vs Data Rate
ADS1288 Shorted Input FFT
PGA gain = 2
Figure 5-10 Shorted Input FFT
ADS1288 Full-Scale Input FFT
PGA gain = 2
Figure 5-12 Full-Scale Input FFT
ADS1288 Channel Crosstalk
AIN2: 31.25Hz, –0.5dBFS signal, AIN1: input shorted measured channel
Figure 5-14 Channel Crosstalk
ADS1288 Offset Error Distribution
30 units
Figure 5-16 Offset Error Distribution
ADS1288 Gain Error Distribution
30 units
Figure 5-18 Gain Error Distribution
ADS1288 Gain Drift Distribution
30 units
Figure 5-20 Gain Drift Distribution
ADS1288 Gain Match Distribution
30 units
Figure 5-22 Gain Match Distribution
ADS1288 THD vs Input Frequency
fIN = 31.25Hz, VIN = –0.5dBFS
Figure 5-24 THD vs Input Frequency
ADS1288 PGA Input Current Noise Distribution
 
Figure 5-26 PGA Input Current Noise Distribution
ADS1288 Buffer Input Current vs Input Voltage
 
Figure 5-28 Buffer Input Current vs Input Voltage
ADS1288 Reference Input Current Distribution
30 units
Figure 5-30 Reference Input Current Distribution
ADS1288 Power-Supply Current Distribution
30 units
Figure 5-32 Power-Supply Current Distribution
ADS1288 PSRR vs Power-Supply Frequency
 
Figure 5-34 PSRR vs Power-Supply Frequency