SBASAW0A February   2024  – November 2025 ADS1288

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements: 1.65V ≤ IOVDD ≤ 1.95V and 2.7V ≤ IOVDD ≤ 3.6V
    7. 5.7 Switching Characteristics: 1.65V ≤ IOVDD ≤ 1.95V and 2.7V ≤ IOVDD ≤ 3.6V
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
      2. 7.3.2 PGA and Buffer
        1. 7.3.2.1 Programmable Gain Amplifier (PGA)
        2. 7.3.2.2 Buffer Operation (PGA Bypass)
      3. 7.3.3 Voltage Reference Input
      4. 7.3.4 IOVDD Power Supply
      5. 7.3.5 Modulator
        1. 7.3.5.1 Modulator Overdrive
      6. 7.3.6 Digital Filter
        1. 7.3.6.1 Sinc Filter Section
        2. 7.3.6.2 FIR Filter Section
        3. 7.3.6.3 Group Delay and Step Response
          1. 7.3.6.3.1 Linear Phase Response
          2. 7.3.6.3.2 Minimum Phase Response
        4. 7.3.6.4 HPF Stage
      7. 7.3.7 Clock Input
      8. 7.3.8 GPIO
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-Down Mode
      2. 7.4.2 Reset
      3. 7.4.3 Synchronization
        1. 7.4.3.1 Pulse-Sync Mode
        2. 7.4.3.2 Continuous-Sync Mode
      4. 7.4.4 Sample Rate Converter
      5. 7.4.5 Offset and Gain Calibration
        1. 7.4.5.1 OFFSET Register
        2. 7.4.5.2 GAIN Register
        3. 7.4.5.3 Calibration Procedure
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. 7.5.1.1 Chip Select (CS)
        2. 7.5.1.2 Serial Clock (SCLK)
        3. 7.5.1.3 Data Input (DIN)
        4. 7.5.1.4 Data Output (DOUT)
        5. 7.5.1.5 Data Ready (DRDY)
      2. 7.5.2 Conversion Data Format
      3. 7.5.3 Commands
        1. 7.5.3.1  Single Byte Command
        2. 7.5.3.2  WAKEUP: Wake Command
        3. 7.5.3.3  STANDBY: Software Power-Down Command
        4. 7.5.3.4  SYNC: Synchronize Command
        5. 7.5.3.5  RESET: Reset Command
        6. 7.5.3.6  Read Data Direct
        7. 7.5.3.7  RDATA: Read Conversion Data Command
        8. 7.5.3.8  RREG: Read Register Command
        9. 7.5.3.9  WREG: Write Register Command
        10. 7.5.3.10 OFSCAL: Offset Calibration Command
        11. 7.5.3.11 GANCAL: Gain Calibration Command
  9. 8 Register Map
    1. 8.1 Register Descriptions
      1. 8.1.1 ID/SYNC: Device ID, SYNC Register (Address = 00h) [Reset = xxxx0010b]
      2. 8.1.2 CONFIG0: Configuration Register 0 (Address = 01h) [Reset = 92h]
      3. 8.1.3 CONFIG1: Configuration Register 1 (Address = 02h) [Reset = 10h]
      4. 8.1.4 HPF0, HPF1: High-Pass Filter Registers (Address = 03h, 04h) [Reset = 32h, 03h]
      5. 8.1.5 OFFSET0, OFFSET1, OFFSET2: Offset Calibration Registers (Address = 05h, 06h, 07h) [Reset = 00h, 00h, 00h]
      6. 8.1.6 GAIN0, GAIN1, GAIN2: Gain Calibration Registers (Address = 08h, 09h, 0Ah) [Reset = 00h, 00h, 40h]
      7. 8.1.7 GPIO: Digital Input/Output Register (Address = 0Bh) [Reset = 000xx000b]
      8. 8.1.8 SRC0, SRC1: Sample Rate Converter Registers (Address = 0Ch, 0Dh) [Reset = 00h, 80h]
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Analog Power Supplies
      2. 9.3.2 Digital Power Supply
      3. 9.3.3 Grounds
      4. 9.3.4 Thermal Pad
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

5.5 Electrical Characteristics

minimum and maximum specifications over –40°C to +85°C; typical specifications are at 25°C; all specifications are at AVDD1 = 5V, AVDD2 = 2.5V to 5V, AVSS = 0V, IOVDD = 1.8V, VREFP = 2.5V, VREFN = 0V,  VCM = 2.5V, PGA gain = 1, RS = 0Ω, fCLK = 4.096MHz and fDATA = 500SPS (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
Input mux on-resistance Input 1 to input 2 cross connection 60 Ω
PGA OPERATION
IB Input current 45 nA
IOS Input offset current ±3 nA
Gain 1, 2, 4, 8, 16, 32, 64 V/V
en-PGA Input voltage noise density PGA Gain = 16 20 nV/√Hz
in-PGA Input current noise density Differential 2.5 pA/√Hz
Antialias filter frequency 30 kHz
BUFFER OPERATION
IB Input current VIN = 2.5V ±0.3 µA
DC PERFORMANCE
en Noise  See Noise Performance section for details
VOS Offset error PGA operation –350/gain - 10 ±30/gain + 5 350/gain + 10 µV
Buffer operation –600 ±50 600
After calibration ±1
Offset error drift PGA operation 0.5/gain µV/°C
Buffer operation 1
Gain error PGA operation, gain = 1 –0.05% ±0.02% 0.05%
After calibration 2 ppm
Buffer operation –0.07% ±0.05% 0.07%
Gain match Relative to PGA gain = 1 –0.2% ±0.06% 0.2%
Gain drift All PGA gains 2 ppm/°C
CMRR Common-mode rejection ratio f = 60Hz 104 120 dB
PSRR Power-supply rejection ratio AVDD2 At dc 80 95 dB
AVSS, AVDD1 At dc 85 110
IOVDD At dc 100 120
AC PERFORMANCE
en-MOD Modulator voltage noise density 100 nV/√Hz
THD Total harmonic distortion
AVDD1 = 3.3V,
AVSS = 0V,
fIN = 31.25Hz,
VIN = –0.5dBFS		 Buffer operation –124 -117 dB
PGA gain = 2 –122
PGA gain = 4 –124 -116
PGA gain = 8 –125
PGA gain = 16 –123 -115
PGA gain = 32 and 64 –124

AVDD1 = 5V,
AVSS = 0V,
fIN = 31.25Hz,
VIN = –0.5dBFS		 Buffer operation –123 -117
PGA gain = 1 –121 -115
PGA gain = 2 –124
PGA gain = 4 –125 -115
PGA gain = 8 –122
PGA gain = 16 –121 -113
PGA gain = 32 and 64 –123
SFDR Spurious-free dynamic range  fIN = 31.25Hz, VIN = –0.5dBFS 115 dB
Crosstalk  fIN = 31.25Hz, VIN = –0.5dBFS –140 dB
VOLTAGE REFERENCE INPUT
Reference input current 80 µA/V
FIR DIGITAL FILTER
fDATA Data rate 125 2000 SPS
Pass-band ripple –0.003 0.003 dB
Pass-band (–0.01dB) 0.375 × fDATA Hz
Bandwidth (–3dB) 0.413 × fDATA Hz
Stop band 0.5 × fDATA Hz
Stop-band attenuation (1) 135 dB
Group delay Minimum phase filter, at dc 5 / fDATA s
Linear phase filter 31/ fDATA
Settling time (latency) Minimum phase filter 62 / fDATA s
Linear phase filter 62 / fDATA
IIR DIGITAL FILTER
High-pass corner frequency 0.1 10 Hz
SAMPLE RATE CONVERTER
Frequency compensation range –244 244 ppm
Resolution 7.45 ppb
DIGITAL INPUT/OUTPUT
VOH High-level output voltage IOH = 1mA 0.8 × IOVDD V
VOL Low-level output voltage IOL = –1mA 0.2 × IOVDD V
Ilkg Input leakage –1 1 μA
POWER SUPPLY
IAVDD1,
IAVSS		 AVDD1, AVSS current AVDD1 = 3.3V PGA operation 0.85 1.1 mA
Buffer operation 0.25 0.45
AVDD1 = 5V PGA operation 0.85 1.1
Buffer operation 0.25 0.45
Power-down mode 1 5 µA
IAVDD2 AVDD2 current AVDD2 = 2.5V 0.7 0.85 mA
Power-down mode 1 5 µA
IIOVDD IOVDD current 0.24 0.4 mA
Power-down mode 1 10 μA
Standby mode 200
IOVDD additional current Sample rate converter operation 0.6 mA
Pd Power dissipation (2) AVDD1 = 3.3V
AVDD2 = 2.5V		 PGA operation 5.0 6.5 mW
Buffer operation 3.0 4.2

AVDD1 = 5V
AVDD2 = 2.5V		 PGA operation 6.4 8.3
Buffer operation 3.4 5.1
(1) Input frequencies at N × 16 kHz ± fDATA / 2 (where N = 1, 2, 3, and so on) intermodulate with the chopper clock. At these frequencies stop band attenuation = –90dBFS (typ).
(2) Excluding current consumed by the voltage reference input or by sample rate converter operation. See voltage reference input current and IOVDD supply current for sample rate converter operation.