SBASB79A November   2024  – February 2026 TAA3020

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements: I2C Interface
    7. 5.7  Switching Characteristics: I2C Interface
    8. 5.8  Timing Requirements: TDM, I2S or LJ Interface
    9. 5.9  Switching Characteristics: TDM, I2S or LJ Interface
    10. 5.10 Timing Requirements: PDM Digital Microphone Interface
    11. 5.11 Switching Characteristics: PDM Digial Microphone Interface
    12. 5.12 Timing Diagrams
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Serial Interfaces
        1. 6.3.1.1 Control Serial Interfaces
        2. 6.3.1.2 Audio Serial Interfaces
          1. 6.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 6.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 6.3.1.2.3 Left-Justified (LJ) Interface
        3. 6.3.1.3 Using Multiple Devices With Shared Buses
      2. 6.3.2  Phase-Locked Loop (PLL) and Clock Generation
      3. 6.3.3  Input Channel Configurations
      4. 6.3.4  Reference Voltage
      5. 6.3.5  Programmable Microphone Bias
      6. 6.3.6  Signal-Chain Processing
        1. 6.3.6.1 Programmable Channel Gain and Digital Volume Control
        2. 6.3.6.2 Programmable Channel Gain Calibration
        3. 6.3.6.3 Programmable Channel Phase Calibration
        4. 6.3.6.4 Programmable Digital High-Pass Filter
        5. 6.3.6.5 Programmable Digital Biquad Filters
        6. 6.3.6.6 Programmable Channel Summer and Digital Mixer
        7. 6.3.6.7 Configurable Digital Decimation Filters
          1. 6.3.6.7.1 Linear Phase Filters
            1. 6.3.6.7.1.1 Sampling Rate: 7.35kHz to 8kHz
            2. 6.3.6.7.1.2 Sampling Rate: 14.7kHz to 16kHz
            3. 6.3.6.7.1.3 Sampling Rate: 22.05kHz to 24kHz
            4. 6.3.6.7.1.4 Sampling Rate: 29.4kHz to 32kHz
            5. 6.3.6.7.1.5 Sampling Rate: 44.1kHz to 48kHz
            6. 6.3.6.7.1.6 Sampling Rate: 88.2kHz to 96kHz
            7. 6.3.6.7.1.7 Sampling Rate: 176.4kHz to 192kHz
            8. 6.3.6.7.1.8 Sampling Rate: 352.8kHz to 384kHz
            9. 6.3.6.7.1.9 Sampling Rate: 705.6kHz to 768kHz
          2. 6.3.6.7.2 Low-Latency Filters
            1. 6.3.6.7.2.1 Sampling Rate: 14.7kHz to 16kHz
            2. 6.3.6.7.2.2 Sampling Rate: 22.05kHz to 24kHz
            3. 6.3.6.7.2.3 Sampling Rate: 29.4kHz to 32kHz
            4. 6.3.6.7.2.4 Sampling Rate: 44.1kHz to 48kHz
            5. 6.3.6.7.2.5 Sampling Rate: 88.2kHz to 96kHz
            6. 6.3.6.7.2.6 Sampling Rate: 176.4kHz to 192kHz
          3. 6.3.6.7.3 Ultra-Low Latency Filters
            1. 6.3.6.7.3.1 Sampling Rate: 14.7kHz to 16kHz
            2. 6.3.6.7.3.2 Sampling Rate: 22.05kHz to 24kHz
            3. 6.3.6.7.3.3 Sampling Rate: 29.4kHz to 32kHz
            4. 6.3.6.7.3.4 Sampling Rate: 44.1kHz to 48kHz
            5. 6.3.6.7.3.5 Sampling Rate: 88.2kHz to 96kHz
            6. 6.3.6.7.3.6 Sampling Rate: 176.4kHz to 192kHz
            7. 6.3.6.7.3.7 Sampling Rate: 352.8kHz to 384kHz
      7. 6.3.7  Automatic Gain Controller (AGC)
      8. 6.3.8  Voice Activity Detection (VAD)
      9. 6.3.9  Digital PDM Microphone Record Channel
      10. 6.3.10 Interrupts, Status, and Digital I/O Pin Multiplexing
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode or Software Shutdown
      2. 6.4.2 Active Mode
      3. 6.4.3 Software Reset
    5. 6.5 Programming
      1. 6.5.1 Control Serial Interfaces
        1. 6.5.1.1 I2C Control Interface
          1. 6.5.1.1.1 General I2C Operation
            1. 6.5.1.1.1.1 I2C Single-Byte and Multiple-Byte Transfers
              1. 6.5.1.1.1.1.1 I2C Single-Byte Write
              2. 6.5.1.1.1.1.2 I2C Multiple-Byte Write
              3. 6.5.1.1.1.1.3 I2C Single-Byte Read
              4. 6.5.1.1.1.1.4 I2C Multiple-Byte Read
  8. 7 Register Maps
    1. 7.1 Device Configuration Registers
    2. 7.2 Page_0 Registers
    3. 7.3 Page_1 Registers
    4. 7.4 Programmable Coefficient Registers
      1. 7.4.1 Programmable Coefficient Registers: Page 2
      2. 7.4.2 Programmable Coefficient Registers: Page 3
      3. 7.4.3 Programmable Coefficient Registers: Page 4
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Two-Channel Analog Microphone Recording
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Example Device Register Configuration Script for EVM Setup
      2. 8.2.2 Four-Channel Digital PDM Microphone Recording
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Example Device Register Configuration Script for EVM Setup
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

6.3.6.7 Configurable Digital Decimation Filters

The device record channel includes a high dynamic range, built-in digital decimation filter to process the oversampled data from the multibit delta-sigma (ΔΣ) modulator to generate digital data at the same Nyquist sampling rate as the FSYNC rate. As illustrated in Figure 6-16, this decimation filter can also be used for processing the oversampled PDM stream from the digital microphone. The decimation filter can be chosen from three different types, depending on the required frequency response, group delay, and phase linearity requirements for the target application. The selection of the decimation filter option can be done by configuring the DECI_FILT (P0_R107_D[5:4]) register bits. Table 6-22 shows the configuration register setting for the decimation filter mode selection for the record channel.

Table 6-22 Decimation Filter Mode Selection for the Record Channel
P0_R107_D[5:4] : DECI_FILT[1:0] DECIMATION FILTER MODE SELECTION
00 (default) Linear phase filters are used for the decimation
01 Low latency filters are used for the decimation
10 Ultra-low latency filters are used for the decimation
11 Reserved (do not use this setting)