SBASB81 December   2024 AFE5401-EP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Digital Characteristics
    7. 5.7  Timing Requirements: Output Interface
    8. 5.8  Timing Requirements: RESET
    9. 5.9  Timing Requirements: Serial Interface Operation
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Timing Requirements: Across Output Serialization Modes
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Low-Noise Amplifier (LNA)
      2. 7.3.2 Programmable Gain Amplifier (PGA)
      3. 7.3.3 Antialiasing Filter
      4. 7.3.4 Analog-to-Digital Converter (ADC)
      5. 7.3.5 Digital Gain
      6. 7.3.6 Input Clock Divider
      7. 7.3.7 Data Output Serialization
      8. 7.3.8 Setting the Input Common-Mode Voltage for the Analog Inputs
        1. 7.3.8.1 Main Channels
        2. 7.3.8.2 Auxiliary Channel
    4. 7.4 Device Functional Modes
      1. 7.4.1 Equalizer Mode
      2. 7.4.2 Data Output Mode
        1. 7.4.2.1 Header
        2. 7.4.2.2 Test Pattern Mode
      3. 7.4.3 Parity
      4. 7.4.4 Standby, Power-Down Mode
      5. 7.4.5 Digital Filtering to Improve Stop-Band Attenuation
        1. 7.4.5.1 Decimate-by-2 Mode
        2. 7.4.5.2 Decimate-by-4 Mode
      6. 7.4.6 Diagnostic Mode
      7. 7.4.7 Signal Chain Probe
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Register Initialization
        1. 7.5.2.1 Register Write Mode
        2. 7.5.2.2 Register Read Mode
      3. 7.5.3 CMOS Output Interface
        1. 7.5.3.1 Synchronization and Triggering
    6. 7.6 Register Maps
      1. 7.6.1 Functional Register Map
      2. 7.6.2 Register Descriptions
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Sequencing
      2. 8.3.2 Power Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Revision History
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  12. 11Mechanical, Packaging, and Orderable Information

7.6.2 Register Descriptions

Figure 7-23 Register 0 (00h)
15141312111098
00000000
76543210
000000REG_READ_
EN		SW_RST
Bits 15:2Must write 0
Bit 1REG_READ_EN: Register read mode
0 = Write (default)
1 = Enable register read
Bit 0SW_RST: Software reset
This bit is the software reset for the entire device. This bit is self-clearing.
Figure 7-24 Register 1 (01h)
15141312111098
00000STDBY00
76543210
DECIMATE_4_ENDIV_REGDIV_FRCDECIMATE_2_ENDIV_ENSE_CLK_
MODE		GLOBAL_PDN
Bits 15:11Must write 0
Bit 10STDBY: Full device standby
0 = Normal (default)
1 = Standby
Bits 9:8Must write 0
Bit 7DECIMATE_4_EN
0 = Decimate-by-4 mode not enabled
1 = Decimate-by-4 mode enabled
The DECIMATE_2_EN and FILT_EN bits must be set.
FIR filter coefficients (C1 to C6) must be written for proper operation.
If the AFE_CLK frequency > 25 MHz, then HF_AFE_CLK_EN must be set.
Bits 6:5DIV_REG: Input clock divider ratio in DIV_FRC mode
DIV_REGfAFE_CLK
0CLKIN ÷ 1Input divider disabled and bypassed
1CLKIN ÷ 2
2CLKIN ÷ 3
3CLKIN ÷ 4
Bit 4DIV_FRC: Force input divider ratio
0 = Auto computed based on CH_OUT_DISx (default). For more details, refer to Table 7-7.
1 = AFE clock frequency is based on DIV_REG settings
Bit 3DECIMATE_2_EN
0 = Normal mode
1 = Decimate-by-2 mode enabled
The FILT_EN bit must be set for proper operation.
FIR filter coefficients (C1 to C6) must be written for proper operation.
If the AFE_CLK frequency > 25 MHz, then HF_AFE_CLK_EN must also be set.
Bit 2DIV_EN: Enable CLKIN divider
0 = Disabled and bypassed (default)
1 = Enabled
Bit 1SE_CLK_MODE: Single-ended input clock configuration
0 = Differential (default)
1 = Single-ended
Bit 0GLOBAL_PDN: Full device power-down
0 = Normal (default)
1 = Global PDN
Figure 7-25 Register 2 (02h)
15141312111098
TST_PAT_MODE00000
76543210
0DGPO0_MODEDGPO1_MODE000
Bits 15:13TST_PAT_MODE: Test pattern for CMOS output
0 = Normal (default)
1 = SYNC
2 = Deskew
3 = Custom register 5[15:0]
4 = All 1s
5 = Toggle
6 = All 0s
7 = Ramp
Bits 12:7Must write 0
Bits 6:5DGPO0_MODE: DGPO0 mode configuration
0 = Low (default)
1 = Parity
2 = Overload
3 = D[11]
Bits 4:3DGPO1_MODE: DGPO1 mode configuration
0 = Low (default)
1 = Parity
2 = Overload
3 = D[11]
Bits 2:0Must write 0
Figure 7-26 Register 3 (03h)
15141312111098
000000TEMP_DATA
76543210
TEMP_DATA
Bits 15:10Ignore bits
Bits 9:0TEMP_DATA: Read-only temperature readout register
Data is 9-bit, twos complement format in degrees Celsius.
Figure 7-27 Register 4 (04h)
15141312111098
OUT_BLANK_HIZOUT_MODE_
EN		DCLK_INVERTTEMP_CONV_ENTEMP_SENS_EN000
76543210
0000OFF_BIN_
DATA_FMT		000
Bit 15OUT_BLANK_HIZ: Output status during blanking phase
0 = D[11:0] and D_GPO[1:0] are low (default) if EN_OUT_MODE = 1
1 = D[11:0] and D_GPO[1:0] are Hi-Z if EN_OUT_MODE = 1
For more details, refer to Figure 7-11.
Bit 14OUT_MODE_EN: Enables output mode gating with DSYNC2
0 = CMOS data is always active (default)
1 = Output mode enabled. Data is transmitted only during sample phase.
Bit 13DCLK_INVERT: Invert DCLK
0 = DCLK rising edge at the center of data (default)
1 = DCLK falling edge at the center of data
Bit 12TEMP_CONV_EN: Enable Temperature Sensor output to digital conversion
0 = Hold conversion
1 = Convert
Bit 11TEMP_SENS_EN: Enable temperature sensor block
0 = Disable temperature sensor
1 = Enable temperature sensor
Bits 10:4Must write 0
Bit 3OFF_BIN_DATA_FMT: Output data format
0 = Twos complement (default)
1 = Offset binary
Bits 2:0Must write 0
Figure 7-28 Register 5 (05h)
15141312111098
CUSTOM_PAT
76543210
CUSTOM_PAT
Bits 15:0CUSTOM_PAT: Custom pattern data
These bits set the custom data pattern.
Figure 7-29 Register 6 (06h)
15141312111098
00000000
76543210
00000DIAG_REG[2:0]
Bits 15:3Ignore bits
Bits 2:0DIAG_REG: Read only diagnostic readout register
DIAG_REG[0] = 0: ADC references are correct
DIAG_REG[1] = 0: Indicates band gap is correct
DIAG_REG[2] = 0: Indicates clock generation is correct
Figure 7-30 Register 7 (07h)
15141312111098
D_GPO_ENPARITY_ODDSTAT_ENDC_INP_ENDC_INP_PROGDIAG_MODE_EN
76543210
0000FILTER_BWHEADER_MODE
Bit 15D_GPO_EN: Enable D_GPO functionality
0 = D_GPO[x] pins are disabled (default)
1 = D_GPO[x] pins are enabled
Bit 14PARITY_ODD: Parity type
0 = Even (default)
1 = Odd
Bit 13STAT_EN: Enable noise and mean calculation of ADC output
0 = Default
1 = Enables noise and mean computation if STAT_CALC_CYCLE is set.
Bit 12DC_INP_EN: Enable dc analog voltage at LNA input. In this mode, equalizer is disabled automatically.
0 = Normal
1 = DC input force is controlled by DC_INP_PROG.
Bits 11:9DC_INP_PROG: DC Input programmability
0 = 0 mV
1 = 0 mV
2 = 50 mV
3 = –50 mV		4 = 100 mV
5 = –100 mV
6 = 100 mV
7 = –100 mV
Bit 8DIAG_MODE_EN: Enable diagnostic mode
0 = Disable diagnostic circuit
1 = Enable diagnostic circuit
Bits 7:4Must write 0
Bits 3:2FILTER_BW: Filter corner frequency
0 = 8 MHz (default)
1 = 7 MHz
2 = 10.5 MHz
3 = 12 MHz
Bits 1:0HEADER_MODE: Header output mode
0 = ADC data at output (default)
1 = Header data at output
2 = [Temperature data, diagnostic data, mean, noise, (-1), (-1), (-1), (-1)]. This data sequence is repeated.
3 = Header data, temperature data, diagnostic data, mean, noise, ADC data.
Refer to Figure 7-14 for more information.
Figure 7-31 Register 8 (08h)
15141312111098
C2_FIR
76543210
DIG_GAIN_C1_FIR
Bits 15:8C2_FIR: Coefficient C2 for FIR digital filter (1)
2 = Default value
Bit 7:0DIG_GAIN_C1_FIR: Digital Gain common for all channels, coefficient C1 for decimation filter
Equation 5. AFE5401-EP

where:

  • (DIG_GAIN + 32) is Mod(2) 128.

Refer to Figure 7-4 for more information.

ModeC1 Functionality
With MULT_ENDIG_GAIN
With DECIMATE_X _ENCoefficient C1 for FIR digital filter
5 = Default value
(1) C1 to C6 FIR filter coefficients are in twos complement form.
(2) Mod = Remainder of the division.
Figure 7-32 Register 9 (09h)
15141312111098
C4_FIR
76543210
C3_FIR
Bits 15:8C4_FIR: Coefficient C4 for FIR digital filter(1)
–2 = Default value
Bit 7:0C3_FIR: Coefficient C3 for FIR digital filter(1)
–13 = Default value
Figure 7-33 Register 10 (0Ah)
15141312111098
C6_FIR
76543210
C5_FIR
Bits 15:8C6_FIR: Coefficient C6 for FIR digital filter(1)
66 = Default value
Bit 7:0C5_FIR: Coefficient C5 for FIR digital filter(1)
38 = Default value
Figure 7-34 Register 15 (0Fh)
15141312111098
00000FAST_DGPO00
76543210
00000000
Bits 15:11,
and Bits 9:0		Must write 0
Bit 10FAST_DGPO: Fast DGPO output buffer
0 = Default strength (default)
1 = Higher drive strength on D_GPO[x] pins.
Must write 0
Figure 7-35 Register 19 (13h)
15141312111098
0OB_DISABLESTR_CTRL_CLKSTR_CTRL_DATA
76543210
STR_CTRL_DATA000000
Bits 15, Bits 5:0Must write 0
Bit 14OB_DISABLE: CMOS output buffers D[11:0], DCLK disabled
0 = Active CMOS output buffers
1 = Hi-Z CMOS output Buffers
Bits 13:10STR_CTRL_CLK: Controls strength of CMOS output DCLK buffer
STR_CTRL_CLKDrive StrengthDRVDD (V)
0Default strength (CLOAD = 5 pF)3.3
6Maximum strength (CLOAD = 15 pF)3.3
5Default strength (CLOAD = 5 pF)1.8
14Maximum strength (CLOAD = 15 pF)1.8
All other options are reserved.
Bit 9:6STR_CTRL_DATA: Controls strength of CMOS output DATA buffers
STR_CTRL_DATADrive StrengthDRVDD (V)
0Default strength (CLOAD = 5 pF)3.3
6Maximum strength (CLOAD = 15 pF)3.3
5Default strength (CLOAD = 5 pF)1.8
14Maximum strength (CLOAD = 15 pF)1.8
All other options are reserved.
Figure 7-36 Register 21 (15h)
15141312111098
DELAY_COUNT[23:16]
76543210
SAMPLE_COUNT[23:16]
Bits 15:8DELAY_COUNT[23:16]: Delay counter, upper bits
These bits determine the delay phase in terms of tAFE_CLK.
DELAY_PHASE = (DELAY_COUNT + 1) × tAFE_CLK.
The valid range for DELAY_COUNT is from 0 to (224 – 2).
The maximum supported values of DELAY_COUNT + SAMPLE_COUNT is (224 – 2).
Bits 7:0SAMPLE_COUNT[23:16]: Sample counter, upper bits
These bits determine the sample phase in terms of tAFE_CLK.
Sample phase = (SAMPLE_COUNT + 1) × tAFE_CLK.
The valid range for SAMPLE_COUNT is from 0 to (224 – 2).
The maximum supported values of DELAY_COUNT + SAMPLE_COUNT is (224 – 2).
Figure 7-37 Register 22 (16h)
15141312111098
DELAY_COUNT[15:0]
76543210
DELAY_COUNT[15:0]
Bits 15:0DELAY_COUNT[15:0]: Delay counter, lower bits
These bits determine the delay phase in terms of tAFE_CLK.
DELAY_PHASE = (DELAY_COUNT + 1) × tAFE_CLK.
The valid range for DELAY_COUNT is from 0 to (224 – 2).
The maximum supported values of DELAY_COUNT + SAMPLE_COUNT is (224 – 2).
Figure 7-38 Register 23 (17h)
15141312111098
SAMPLE_COUNT[15:0]
76543210
SAMPLE_COUNT[15:0]
Bits 15:0SAMPLE_COUNT[15:0]: Sample counter, lower bits
These bits determine the sample phase in terms of tAFE_CLK.
Sample phase = (SAMPLE_COUNT + 1) × tAFE_CLK.
The valid range for SAMPLE_COUNT is from 0 to (224 – 2).
The maximum supported values of DELAY_COUNT + SAMPLE_COUNT is (224 – 2).
Figure 7-39 Register 24 (18h)
15141312111098
TRIG_FALLDSYNC1_
START_LOW		0DSYNC_EN0COMP_DSYNC1[15:6]
76543210
COMP_DSYNC1[15:6]0
Bit 15TRIG_FALL
0 = TRIG event on the TRIG rising edge
1 = TRIG event on the TRIG falling edge
Bit 14DSYNC1_START_LOW: Selects DSYNC1 start level
0 = DSYNC1 starts with logic high (default)
1 = DSYNC1 starts with logic low
Bit 13Must write 0
Bit 12DSYNC_EN: Enable DSYNC1/2 generation
0 = Disable DSYNC1/2 signals (default - logic low)
1 = Enable DSYNC1/2 signals
Bit 11Must write 0
Bits 10:1COMP_DSYNC1[15:6]: DSYNC1, upper bits
These bits determine the DSYNC1 period in the number of tAFE_CLK cycles. For COMP_DSYNC1 = 0 or 1, DSYNC1 is static.
Bit 0Must write 0
Figure 7-40 Register 25 (19h)
15141312111098
COMP_DSYNC1[5:0]00
76543210
DSYNC2_LOW[23:16]
Bits 15:10COMP_DSYNC1[5:0]: DSYNC1, lower bits
These bits determine the DSYNC1 period in the number of tAFE_CLK cycles. For COMP_DSYNC1 = 0 or 1, DSYNC1 is static.
Bits 9:8Must write 0
Bits 7:0DSYNC2_LOW[23:16]: DSYNC2, upper bits
Low pulse duration of DSYNC2 in number of tAFE_CLK clocks.
Figure 7-41 Register 26 (1Ah)
15141312111098
DSYNC2_LOW[15:0]
76543210
DSYNC2_LOW[15:0]
Bits 15:0DSYNC2_LOW[15:0]: DSYNC2, lower bits
Low pulse duration of DSYNC2 in number of tAFE_CLK clocks.
Figure 7-42 Register 27 (1Bh)
15141312111098
DSYNC1_HIGH
76543210
DSYNC1_HIGH
Bits 15:0DSYNC1_HIGH: DSYNC1
High pulse duration of DSYNC1, in number of tAFE_CLK clocks.
DSYNC1 high = high for [(DSYNC1_HI + COMP_DSYNC1 ÷ 2) Mod (1) COMP_DSYNC1]
(1) Mod = Remainder of the division
Figure 7-43 Register 29 (1Dh)
15141312111098
OFFSET_DIS0STAT_CH_SEL00STAT_CALC_CYCLE
76543210
STAT_CALC_CYCLE0000STAT_CH_AUTO_SEL
Bit 15OFFSET_DIS: Bypass OFFSET addition at channel output
0 = Default. The OFFSET_CHx register value is added to the channel output.
1 = Disable OFFSET. The OFFSET_CHx register value is not added to the channel output.
Bit 14Always write 0
Bits 13:12STAT_CH_SEL: Manual channel selection for computation by STAT module
0 = Channel 1
1 = Channel 2
2 = Channel 3
3 = Channel 4
Bits 11:10Always write 0
Bits 9:5STAT_CALC_CYCLE
Number of ADC samples used for STAT computation = 2STAT_CALC_CYCLE+1, STAT_CALC_CYCLE range = 0 to 30
and Bits 4:1Always write 0
Bit 0STAT_CH_AUTO_SEL: Automatic channel selection for SNR Computation
0 = Static, computation is done based on the STAT_CH_SEL selection
1 = Auto, computation is sequentially done for all four channels
Figure 7-44 Register 30 (1Eh)
15141312111098
0000000MULT_EN
76543210
FILT_EN0000000
Bits 15:9Must write 0
Bit 8MULT_EN: Channel multiplier enable
0 = Disable multiplier
1 = Enable multiplier. For digital gain, DIG_GAIN_C1_FIR must be written.
Bit 7FILT_EN: Digital decimation filter enable
0 = Disable filter
1 = Enable standard 11-tap, symmetric FIR digital filter.
Bits 6:0Must write 0
Figure 7-45 Register 32 (20h)
15141312111098
0000HEADER_CH1
76543210
HEADER_CH1
Bits 15:12Must write 0
Bits 11:0HEADER_CH1: Header information for channel 1
These bits provide the header information for channel 1.
Figure 7-46 Register 33 (21h)
15141312111098
CH_OUT_DIS1AUX_CH1_ENPDN_CH1INVERT_ CH100OFFSET_CH1
76543210
OFFSET_CH1
Bit 15CH_OUT_DIS1: Channel 1 disable
Channel 1 is not muxed out.
0 = Channel 1 is output (default)
1 = Channel 1 is not output
Bit 14AUX_CH1_EN: Enable auxiliary channel for channel 1
0 = Filter (default)
1 = Auxiliary
Bit 13PDN_CH1: Power-down channel 1
0 = Active (default)
1 = Power-down
Bit 12INVERT_CH1: Invert channel 1 output
0 = Normal ouput (default)
1 = Inverted output
Bits 11:10Must write 0
Bits 9:0OFFSET_CH1: Output offset of channel 1 range
Output offset value = OFFSET_CH1 ÷ 4, output offset value is added to channel output.
Figure 7-47 Register 34 (22h)
15141312111098
00MEAN_CH1
76543210
MEAN_CH1
Bits 15:14Must write 0
Bits 13:0MEAN_CH1: Mean for channel 1 (read-only register)
These bits provide the mean information computed by STAT module for channel 1.
Figure 7-48 Register 35 (23h)
15141312111098
00NOISE_CH1
76543210
NOISE_CH1
Bits 15:14Must write 0
Bits 13:0NOISE_CH1: Noise for channel 1 (read-only register)
These bits provide the noise information computed by STAT module for channel 1.
Figure 7-49 Register 36 (24h)
15141312111098
0000HEADER_CH2
76543210
HEADER_CH2
Bits 15:12Must write 0
Bits 11:0HEADER_CH2: Header information for channel 2
These bits provide the header information for channel 2.
Figure 7-50 Register 37 (25h)
15141312111098
CH_OUT_DIS2AUX_CH2_ENPDN_CH2INVERT_CH200OFFSET_CH2
76543210
OFFSET_CH2
Bit 15CH_OUT_DIS2: Channel 2 disable
Channel 2 is not muxed out.
0 = Channel 2 is output (default)
1 = Channel 2 is not output
Bit 14AUX_CH2_EN: Enable auxiliary channel for channel 2
0 = Filter (default)
1 = Auxiliary
Bit 13PDN_CH2: Power-down channel 2
0 = Active (default)
1 = Power-down
Bit 12INVERT_CH2: Invert channel 2 output
0 = Normal (default)
1 = Inverted output
Bits 11:10Must write 0
Bits 9:0OFFSET_CH2: Output offset of Channel 2
Output offset value = OFFSET_CH2 ÷ 4, output offset value is added to the channel output
Figure 7-51 Register 38 (26h)
15141312111098
00MEAN_CH2
76543210
MEAN_CH2
Bits 15:14Must write 0
Bits 13:0MEAN_CH2: Mean for channel 2 (read-only register)
These bits provide the mean information computed by the STAT module for channel 2.
Figure 7-52 Register 39 (27h)
15141312111098
00NOISE_CH2
76543210
NOISE_CH2
Bits 15:14Must write 0
Bits 13:0NOISE_CH2: Noise for channel 2 (read-only register)
These bits provide the noise information computed by the STAT module for channel 2.
Figure 7-53 Register 40 (28h)
15141312111098
0000HEADER_CH3
76543210
HEADER_CH3
Bits 15:12Must write 0
Bits 11:0HEADER_CH3: Header information for channel 3
These bits provide the header information for channel 3.
Figure 7-54 Register 41 (29h)
15141312111098
CH_OUT_DIS3AUX_CH3_ENPDN_CH3INVERT_CH300OFFSET_CH3
76543210
OFFSET_CH3
Bit 15CH_OUT_DIS3: Channel 3 disable
Channel 3 is not muxed out.
0 = Channel 3 is output (default)
1 = Channel 3 is not output
Bit 14AUX_CH3_EN: Enable auxiliary channel for channel 3
0 = Filter (default)
1 = Auxiliary
Bit 13PDN_CH3: Power-down channel 3
0 = Active (default)
1 = Power-down
Bit 12INVERT_CH3: Invert channel 3 output
0 = Normal (default)
1 = Inverted output
Bits 11:10Must write 0
Bits 9:0OFFSET_CH3: Output offset of Channel 3
Output offset value = OFFSET_CH3 ÷ 4, output offset value is added to the channel output
Figure 7-55 Register 42 (2Ah)
15141312111098
00MEAN_CH3
76543210
MEAN_CH3
Bits 15:14Must write 0
Bits 13:0MEAN_CH3: Mean for channel 3 (read-only register)
These bits provide the mean information computed by the STAT module for channel 3.
Figure 7-56 Register 43 (2Bh)
15141312111098
00NOISE_CH3
76543210
NOISE_CH3
Bits 15:14Must write 0
Bits 13:0NOISE_CH3: Noise for channel 3 (read-only register)
These bits provide the noise information computed by the STAT module for channel 3.
Figure 7-57 Register 44 (2Ch)
15141312111098
0000HEADER_CH4
76543210
HEADER_CH4
Bits 15:12Must write 0
Bits 11:0HEADER_CH4: Header information for channel 4
These bits provide the header information for channel 4.
Figure 7-58 Register 45 (2Dh)
15141312111098
CH_OUT_DIS4AUX_CH4_ENPDN_CH4INVERT_CH400OFFSET_CH4
76543210
OFFSET_CH4
Bit 15CH_OUT_DIS1: Channel 4 disable
Channel 4 is not muxed out.
0 = Channel 4 is output (default)
1 = Channel 4 is not output
Bit 14AUX_CH4_EN: Enable auxiliary channel for channel 4
0 = Filter (default)
1 = Auxiliary
Bit 13PDN_CH4: Power-down channel 4
0 = Active (default)
1 = Power-down
Bit 12INVERT_CH4: Invert channel 4 output
0 = Normal (default)
1 = Inverted output
Bits 11:10Must write 0
Bits 9:0OFFSET_CH4: Output offset of channel 4
Output offset value = OFFSET_CH4 ÷ 4, output offset value is added to the channel output
Figure 7-59 Register 46 (2Eh)
15141312111098
00MEAN_CH4
76543210
MEAN_CH4
Bits 15:14Must write 0
Bits 13:0MEAN_CH4: Mean for channel 4 (read-only register)
These bits provide the mean information computed by the STAT module for channel 4.
Figure 7-60 Register 47 (2Fh)
15141312111098
00NOISE_CH4
76543210
NOISE_CH4
Bits 15:14Must write 0
Bits 13:0NOISE_CH4: Noise for channel 4 (read-only register)
These bits provide the noise information computed by the STAT module for channel 4.
Figure 7-61 Register 65 (41h)
15141312111098
00000TERM_INT_
20K_AUX		00
76543210
00000000
Bits 15:11Must write 0
Bit 10TERM_INT_20K_AUX: Auxiliary input termination
This bit is common for all channels. This bit provides an auxiliary input internal differential termination of 20 kΩ.
0 = 2-kΩ differential resistance (default)
1 = 20-kΩ differential resistance
Bits 9:0Must write 0
Figure 7-62 Register 69 (45h)
15141312111098
TERM_INT_
20K_LNA		LNA_GAINPGA_GAIN
76543210
PGA_GAINEQ_EN000000
Bit 15TERM_INT_20K_LNA: LNA input termination
This bit is common for all channels. This bit provides LNA input internal differential termination of 20 kΩ.
0 = 2-kΩ differential resistance (default)
1 = 20-kΩ differential resistance
Bits 14:13LNA_GAIN: LNA gain
These bits are common for all channels.
0 = 15 dB (default)
1 = 18 dB
2 = 12 dB
3 = 16.5 dB
Bits 12:7PGA_GAIN: PGA gain
These bits are common for all channels. PGA gain = 0 dB, 3 dB, 6 dB, 9 dB, 12 dB, 15 dB, 18 dB, 21 dB, 24 dB, 27 dB, and 30 dB.
0 = 0 dB
1 = 3 dB
2 = 6 dB
3 = 9 dB
4 = 12 dB
5 = 15 dB		6 = 18 dB
7 = 21 dB
8 = 24 dB
9 = 27 dB
10 = 30 dB

Bit 6EQ_EN: Equalizer enable
These bits are common for all channels.
0 = Disabled (default)
1 = Enabled
Bits 5:0Must write 0
Figure 7-63 Register 70 (46h)
15141312111098
0HPL_EN000000
76543210
000000VOUT_ON_ADC
Bit 15Must write 0
Bit 14HPL_EN: High-performance linearity mode
0 = Default
1 = Improves linearity (HD3) with increased power dissipation
Bits 13:2Must write 0
Bits 1:0VOUT_ON_ADC: Check analog block output on ADC input
0 = LNA + antialiasing filter + ADC (default)
1 = LNA + ADC
2 = AMP1 + ADC
3 = AMP2 + ADC
Figure 7-64 Register 71 (47h)
15141312111098
00000000
76543210
0000HIGH_POW_
LNA		EQ_EN_LOW_
FC		00
Bits 15:4Must write 0
Bit 3HIGH_POW_LNA
0 = Default mode
1 = High-power LNA improves channel input-referred noise at high LNA and PGA gains compared to default mode. This mode increases power dissipation.
Bit 2EQ_EN_LOW_FC: Enable Equalizer Low Frequency Corner Frequency
0 = Disable
1 = Enable; EQ_EN must also be enabled for this mode
Bits 1:0Must write 0
Figure 7-65 Register 100 (64h)
15141312111098
0HF_AFE_CLK_EN00000
76543210
00000000
Bits 15Must write 0
Bits 14:13HF_AFE_CLK_EN
0 = Default
3 = For fAFE_CLK > 25 MHz ( in decimation modes)
Bits 12:0Must write 0