SBASB82 May   2025 ADS9127 , ADS9128 , ADS9129

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements
    7. 5.7  Switching Characteristics
    8. 5.8  Timing Diagrams
    9. 5.9  Typical Characteristics: All Devices
    10. 5.10 Typical Characteristics: ADS9129
    11. 5.11 Typical Characteristics: ADS9128
    12. 5.12 Typical Characteristics: ADS9127
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
      2. 6.3.2 Analog Input Bandwidth
      3. 6.3.3 ADC Transfer Function
      4. 6.3.4 Reference Voltage
      5. 6.3.5 Temperature Sensor
      6. 6.3.6 Data Averaging
      7. 6.3.7 Digital Down Converter
      8. 6.3.8 Data Interface
        1. 6.3.8.1 Data Frame Width
        2. 6.3.8.2 Synchronizing Multiple ADCs
        3. 6.3.8.3 Test Patterns for Data Interface
          1. 6.3.8.3.1 Fixed Pattern
          2. 6.3.8.3.2 Alternating Test Pattern
          3. 6.3.8.3.3 Digital Ramp
      9. 6.3.9 ADC Sampling Clock Input
    4. 6.4 Device Functional Modes
      1. 6.4.1 Reset
      2. 6.4.2 Power-Down Options
      3. 6.4.3 Normal Operation
      4. 6.4.4 Initialization Sequence
    5. 6.5 Programming
      1. 6.5.1 Register Write
      2. 6.5.2 Register Read
      3. 6.5.3 Multiple Devices: Daisy-Chain Topology for SPI Configuration
        1. 6.5.3.1 Register Write With Daisy-Chain
        2. 6.5.3.2 Register Read With Daisy-Chain
  8. 7 Register Map
    1. 7.1 Register Bank 0
    2. 7.2 Register Bank 1
    3. 7.3 Register Bank 2
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Data Acquisition (DAQ) Circuit for a ≤20kHz Input Signal Bandwidth
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Data Acquisition (DAQ) Circuit for a ≤100kHz Input Signal Bandwidth
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Application Curves
      3. 8.2.3 Data Acquisition (DAQ) Circuit for a ≤1MHz Input Signal Bandwidth
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

5.7 Switching Characteristics

at AVDD_5V = 4.75V to 5.25V for ADS9129, and ADS9128, and AVDD_5V = 4.5V to 5.5V for ADS9127, VDD_1V8 = 1.75V to 1.85V, internal VREF = 4.096V, and maximum throughput (unless otherwise noted); minimum and maximum values at TA = –40°C to +125°C; typical values at TA = 25°C
PARAMETER TEST CONDITIONS MIN MAX UNIT
RESET
tPU Power-up time for device 25 ms
LVDS DATA INTERFACE
tRT Rise time With 50Ω transmission line of length = 20mm, differential RL = 100Ω, and CL = 1pF 600 ps
tFT Fall time 600 ps
tCYCLE Sampling clock period ADS9129 50 ns
ADS9128 100
ADS9127 200
tDCLK Clock output 4.167 ns
Clock duty cycle 45 55 %
td_DCLKDO Time delay: DCLKP rising to corresponding data valid SDR mode  –0.35 0.35 ns
toff_DCLKDO_r Time offset: DCLKP rising to corresponding data valid DDR mode tDCLK / 4 – 0.35 tDCLK / 4 + 0.35 ns
toff_DCLKDO_f Time offset: DCLKP falling to corresponding data valid DDR mode tDCLK / 4 – 0.35 tDCLK / 4 + 0.35 ns
tPD Time delay: SMPL_CLK falling to DCLKP rising tDCLK ns
tPU_SMPL_CLK Time delay: Free-running clock connected to SMPL_CLK to ADC data valid 100 µs
tLAT(1) Time delay: Internal digital delay to MSB of data output 3 12 ns
SPI TIMINGS
tden_CKDO Time delay: 8th SCLK rising edge to SDO enable 30 ns
tdz_CKDO Time delay: 24th SCLK rising edge to SDO going Hi-Z 30 ns
td_CKDO Time delay: SCLK launch edge to corresponding data valid on SDO 30 ns
tht_CKDO Hold time: SCLK launch edge to previous data valid on SDO 2 ns
(1) See section on ADC Sampling Clock Input for more details on data output latency.