SBASB89 May   2025 ADS117L14 , ADS117L18

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 IMD Measurement
    12. 6.12 SFDR Measurement
    13. 6.13 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs (AINP, AINN)
        1. 7.3.1.1 Input Range
      2. 7.3.2 Reference Voltage (REFP, REFN)
        1. 7.3.2.1 Reference Voltage Range
      3. 7.3.3 Clock Operation
        1. 7.3.3.1 Clock Dividers
        2. 7.3.3.2 Internal Oscillator
        3. 7.3.3.3 External Clock
      4. 7.3.4 Power-On Reset (POR)
      5. 7.3.5 VCM Output Voltage
      6. 7.3.6 GPIO
      7. 7.3.7 Modulator
      8. 7.3.8 Digital Filter
        1. 7.3.8.1 Wideband Filter
        2. 7.3.8.2 Low-Latency Filter (Sinc)
          1. 7.3.8.2.1 Sinc4 Filter
          2. 7.3.8.2.2 Sinc4 + Sinc1 Cascade Filter
          3. 7.3.8.2.3 Sinc3 Filter
          4. 7.3.8.2.4 Sinc3 + Sinc1 Filter
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset
        1. 7.4.1.1 RESET Pin
        2. 7.4.1.2 Reset by SPI Register
        3. 7.4.1.3 Reset by SPI Input Pattern
      2. 7.4.2 Idle and Standby Modes
      3. 7.4.3 Power-Down
      4. 7.4.4 Speed Modes
      5. 7.4.5 Synchronization
        1. 7.4.5.1 Synchronized Control Mode
        2. 7.4.5.2 Start/Stop Control Mode
      6. 7.4.6 Conversion-Start Delay Time
      7. 7.4.7 Calibration
        1. 7.4.7.1 Offset Calibration Registers
        2. 7.4.7.2 Gain Calibration Registers
        3. 7.4.7.3 Calibration Procedure
      8. 7.4.8 Diagnostics
        1. 7.4.8.1 ERROR Pin and ERR_FLAG Bit
        2. 7.4.8.2 SPI CRC
        3. 7.4.8.3 Register Map CRC
        4. 7.4.8.4 ADC Error
        5. 7.4.8.5 SPI Address Range
        6. 7.4.8.6 SCLK Counter
        7. 7.4.8.7 Clock Counter
        8. 7.4.8.8 Frame-Sync CRC
        9. 7.4.8.9 Self Test
      9. 7.4.9 Frame-Sync Data Port
        1. 7.4.9.1  Data Packet
        2. 7.4.9.2  Data Format
        3. 7.4.9.3  STATUS_DP Header Byte
        4. 7.4.9.4  FSYNC Pin
        5. 7.4.9.5  DCLK Pin
        6. 7.4.9.6  DOUTx Pins
        7. 7.4.9.7  DINx Pins
        8. 7.4.9.8  Time Division Multiplexing
        9. 7.4.9.9  Daisy Chain
        10. 7.4.9.10 DOUTx Timing
    5. 7.5 Programming
      1. 7.5.1 Hardware Programming
      2. 7.5.2 SPI Programming
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output (SDO)
      3. 7.5.3 SPI Frame
      4. 7.5.4 Commands
        1. 7.5.4.1 Write Register Command
        2. 7.5.4.2 Read Register Command
      5. 7.5.5 SPI Daisy-Chain
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Driver
      2. 9.1.2 Anti-alias Filter
      3. 9.1.3 Reference Voltage
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 AVDD1 and AVSS
      2. 9.3.2 AVDD2
      3. 9.3.3 IOVDD
      4. 9.3.4 CAPA and CAPD
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

6.13 Noise Performance

The ADCs offer four speed modes with programmable OSR allowing trade-offs between power consumption and bandwidth. The modes are max speed, high speed, mid speed, and low speed, with decreasing levels of device power consumption and signal bandwidth.

With the ADC inputs shorted, the output code is a single value or flickering codes between two or more values. Code flicker depends on the ADC noise for the selected OSR value and the dc signal relative to the next code transition. The ADC peak-to-peak noise value is typically 6.6 × the RMS noise value. Code flicker results when the amplitude of noise is large enough to trigger code transitions.

The quantization error of an ADC is ±0.5 LSB. For an ac signal, the quantization error becomes a quantization noise. Figure 6-1 shows the quantization error converting to noise (LSB error plot) as the signal changes. For non-coherent sampling, this quantization noise is approximated as white noise, spread evenly across the frequency band. For an N-bit ADC, the signal-to-quantization noise ratio (SQNR) is as follows: SQNR (dB) = 6.02 x N + 1.76. For a 16-bit ADC, SQNR is 98.1dB.

ADS117L14 ADS117L18 Quantization Noise of Sine Wave Input Figure 6-1 Quantization Noise of Sine Wave Input

Table 7-7 through Table 6-5 summarize noise performance. SNR values in the tables are calculated by the ratio of the RMS full scale range to the root-sum-square result of ADC thermal noise and 16-bit quantization noise. For this device, the value of quantization noise is typically greater than thermal noise, therefore SNR is limited to 98.1dB for large values of OSR.

Table 6-1 Wideband Filter Noise Performance (VREF = 4.096V, 1x Input Range)
MODE fCLK
(MHz)		 OSR DATA RATE
(kSPS)		 NOISE
(en, µVRMS)		 SNR
(dB)
Max speed 32.768 32 512 10.9 97.7
High speed 25.6 400 10.8 97.7
Mid speed 12.8 200 10.5 97.8
Low speed 3.2 50 10.4 97.8
Max speed 32.768 64 256 7.48 97.9
High speed 25.6 200 7.33 97.9
Mid speed 12.8 100 7.21 97.9
Low speed 3.2 25 7.17 97.9
Max speed 32.768 128 128 5.17 98.0
High speed 25.6 100 5.14 98.0
Mid speed 12.8 50 5.02 98.0
Low speed 3.2 12.5 5.02 98.0
Max speed 32.768 256 64 3.64 98.1
High speed 25.6 50 3.59 98.1
Mid speed 12.8 25 3.55 98.1
Low speed 3.2 6.25 3.55 98.1
Max speed 32.768 512 32 2.56 98.1
High speed 25.6 25 2.55 98.1
Mid speed 12.8 12.5 2.49 98.1
Low speed 3.2 3.125 2.49 98.1
Max speed 32.768 1024 16 1.73 98.1
High speed 25.6 12.5 1.80 98.1
Mid speed 12.8 6.25 1.73 98.1
Low speed 3.2 1.5625 1.75 98.1
Max speed 32.768 2048 8 1.37 98.1
High speed 25.6 6.25 1.28 98.1
Mid speed 12.8 3.125 1.26 98.1
Low speed 3.2 0.78125 1.26 98.1
Max speed 32.768 4096 4 0.93 98.1
High speed 25.6 3.125 0.92 98.1
Mid speed 12.8 1.5625 0.90 98.1
Low speed 3.2 0.390625 0.89 98.1
Table 6-2 Sinc4 Filter Noise Performance (VREF = 4.096V, 1x Input Range)
MODE fCLK
(MHz)		 OSR DATA RATE
(kSPS)		 NOISE
(en, µVRMS)		 SNR
(dB)
Max speed 32.768 12 1365.3 65.1 91.9
High speed 25.6 1066.6 66.1 91.8
Mid speed 12.8 533.3 65.3 91.9
Low speed 3.2 133.33 65.3 91.9
Max speed 32.768 16 1024 25.1 96.4
High speed 25.6 800 25.1 96.4
Mid speed 12.8 400 24.6 96.5
Low speed 3.2 100 24.7 96.5
Max speed 32.768 24 682.67 10.4 97.8
High speed 25.6 533.3 10.3 97.8
Mid speed 12.8 266.67 10.1 97.8
Low speed 3.2 66.67 10.1 97.8
Max speed 32.768 32 512 8.05 97.9
High speed 25.6 400 7.83 97.9
Mid speed 12.8 200 7.78 97.9
Low speed 3.2 50 7.76 97.9
Max speed 32.768 64 256 5.46 98.0
High speed 25.6 200 5.44 98.0
Mid speed 12.8 100 5.30 98.0
Low speed 3.2 25 5.30 98.0
Max speed 32.768 128 128 3.79 98.1
High speed 25.6 100 3.76 98.1
Mid speed 12.8 50 3.68 98.1
Low speed 3.2 12.5 3.62 98.1
Max speed 32.768 256 64 2.74 98.1
High speed 25.6 50 2.69 98.1
Mid speed 12.8 25 2.63 98.1
Low speed 3.2 6.25 2.62 98.1
Max speed 32.768 512 32 1.90 98.1
High speed 25.6 25 1.89 98.1
Mid speed 12.8 12.5 1.86 98.1
Low speed 3.2 3.125 1.84 98.1
Max speed 32.768 1024 16 1.34 98.1
High speed 25.6 12.5 1.34 98.1
Mid speed 12.8 6.25 1.33 98.1
Low speed 3.2 1.56 1.32 98.1
Max speed 32.768 2048 8 0.98 98.1
High speed 25.6 6.25 0.95 98.1
Mid speed 12.8 3.125 0.93 98.1
Low speed 3.2 0.78 0.92 98.1
Max speed 32.768 4096 4 0.70 98.1
High speed 25.6 3.125 0.69 98.1
Mid speed 12.8 1.563 0.66 98.1
Low speed 3.2 0.39 0.66 98.1
Table 6-3 Sinc4 + Sinc1 Filter Performance (VREF = 4.096V, 1x Input Range)
MODE fCLK
(MHz)		 OSR DATA RATE
(kSPS)		 NOISE (en)
(µVRMS)		 SNR
(dB)
Max speed 32.768 64 256 6.77 98.0
High speed 25.6 200 6.62 98.0
Mid speed 12.8 100 6.60 98.0
Low speed 3.2 25 6.50 98.0
Max speed 32.768 128 128 5.16 98.0
High speed 25.6 100 5.13 98.0
Mid speed 12.8 50 5.07 98.0
Low speed 3.2 12.5 5.02 98.0
Max speed 32.768 320 51.2 3.39 98.1
High speed 25.6 40 3.35 98.1
Mid speed 12.8 20 3.29 98.1
Low speed 3.2 5 3.28 98.1
Max speed 32.768 640 25.6 2.42 98.1
High speed 25.6 20 2.39 98.1
Mid speed 12.8 10 2.35 98.1
Low speed 3.2 2.5 2.36 98.1
Max speed 32.768 1280 12.8 1.74 98.1
High speed 25.6 10 1.73 98.1
Mid speed 12.8 5 1.69 98.1
Low speed 3.2 1.25 1.68 98.1
Max speed 32.768 3200 5.12 1.10 98.1
High speed 25.6 4 1.09 98.1
Mid speed 12.8 2 1.07 98.1
Low speed 3.2 0.5 1.07 98.1
Max speed 32.768 6400 2.56 0.79 98.1
High speed 25.6 2 0.78 98.1
Mid speed 12.8 1 0.77 98.1
Low speed 3.2 0.25 0.77 98.1
Max speed 32.768 12800 1.28 0.57 98.1
High speed 25.6 1 0.56 98.1
Mid speed 12.8 0.5 0.55 98.1
Low speed 3.2 0.125 0.54 98.1
Max speed 32.768 32000 0.512 0.37 98.1
High speed 25.6 0.4 0.37 98.1
Mid speed 12.8 0.2 0.37 98.1
Low speed 3.2 0.05 0.37 98.1
Table 6-4 Sinc3 Filter Performance (VREF = 4.096V, 1x Input Range)
MODE fCLK
(MHz)		 OSR DATA RATE
(SPS)		 NOISE (en)
(µVRMS) 		SNR
(dB)
Max speed 32.768 26667 614.4 0.32 98.1
High speed 25.6 480 0.32 98.1
Mid speed 12.8 240 0.32 98.1
Low speed 3.2 60 0.32 98.1
Max speed 32.768 32000 512 0.32 98.1
High speed 25.6 400 0.31 98.1
Mid speed 12.8 200 0.31 98.1
Low speed 3.2 50 0.31 98.1
Table 6-5 Sinc3 + Sinc1 Filter Performance (VREF = 4.096V, 1x Input Range)
MODE fCLK
(MHz)		 OSR DATA RATE
(SPS)		 NOISE (en)
(µVRMS) 		SNR
(dB)
Max speed 32.768 96000 170.6 0.25 98.1
High speed 25.6 133.3 0.25 98.1
Mid speed 12.8 66.6 0.25 98.1
Low speed 3.2 16.6 0.25 98.1
Max speed 32.768 160000 102.4 0.24 98.1
High speed 25.6 80 0.25 98.1
Mid speed 12.8 40 0.25 98.1
Low speed 3.2 10 0.25 98.1