The ADS117L14 (quad) and ADS117L18 (octal) are 16-bit, delta-sigma (ΔΣ), analog-to-digital converters (ADCs). The devices provide simultaneous sampling of four or eight channels with data rates up to 512kSPS (wideband filter mode) and 1365kSPS (low-latency filter mode). The 24-bit ADS127L14 (quad) and ADS127L18 (octal) ADCs are pin-compatible devices for increased resolution.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | ADS117L1x 512kSPS, Quad and Octal, Simultaneous-Sampling, 16-Bit ΔΣ ADCs datasheet | PDF | HTML | 23 May 2025 |
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Calculator installer
General calculator tool for analog design support.
Github™
Example FPGA code for ADS127L18 data port
This is an example of how to latch data from the ADS127L18 frame-sync data port that outputs the channel conversion data. The data port is a synchronous, read-only interface with synchronized output clock signals (FSYNC and DCLK) and channel data (DOUTx). This Verilog module captures and splits the continuous 1/2/4/8 lane data (including STATUS and CRC bytes if enabled) into eight separate channels and latches the data between frames.
Github™
Example C code for MSPM0 + ADS127L18
Prototype your microcontroller solution for interfacing with the ADS127L18 product family. This example code project uses the MSPM0 to configure the ADS127L18 EVM and record conversion via an SPI peripheral.