SBOS061D February   1997  – December 2025 XTR105

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Linearization
        1. 6.3.1.1 High-Resistance RTDs
      2. 6.3.2 Voltage Regulator
      3. 6.3.3 Open-Circuit Protection
      4. 6.3.4 Reverse-Voltage Protection
      5. 6.3.5 Surge Protection
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 External Transistor
      2. 7.1.2 Loop Power Supply
      3. 7.1.3 2-Wire and 3-Wire RTD Connections
      4. 7.1.4 Radio Frequency Interference
      5. 7.1.5 Error Analysis
    2. 7.2 Typical Applications
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Device Support
        1. 8.1.1.1 Device Nomenclature
      2. 8.1.2 Related Documentation
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

5.5 Typical Characteristics

at TA = +25°C and V+ = 24V, and all chip site origin (CSO), (unless otherwise noted)

XTR105 Transconductance vs Frequency
 
Figure 5-1 Transconductance vs Frequency
XTR105 Step Response, RG = 125Ω, 2kΩ
CSO: TID
 
Figure 5-3 Step Response, RG = 125Ω, 2kΩ
XTR105 Power-Supply Rejection vs Frequency
 
Figure 5-5 Power-Supply Rejection vs Frequency
XTR105 Underscale Current vs Temperature
 
Figure 5-7 Underscale Current vs Temperature
XTR105 Zero Output and Reference Current Noise vs Frequency
 
Figure 5-9 Zero Output and Reference Current Noise vs Frequency
XTR105 Input Bias and Offset Current vs Temperature
CSO: TID
 
Figure 5-11 Input Bias and Offset Current vs Temperature
XTR105 Input Offset Voltage Drift Production Distribution
CSO: SHE
 
Figure 5-13 Input Offset Voltage Drift Production Distribution
XTR105 Zero Output Drift Production Distribution
 
Figure 5-15 Zero Output Drift Production Distribution
XTR105 Current Source Matching Drift Production Distribution
 
Figure 5-17 Current Source Matching Drift Production Distribution
XTR105 Reference Current Error vs Temperature
 
Figure 5-19 Reference Current Error vs Temperature
XTR105 Step Response
CSO: SHE
 
Figure 5-2 Step Response
XTR105 Common-Mode Rejection vs Frequency
 
Figure 5-4 Common-Mode Rejection vs Frequency
XTR105 Overscale Current vs Temperature
With external transistor
 
Figure 5-6 Overscale Current vs Temperature
XTR105 Input Voltage and Current Noise Density vs Frequency
 
Figure 5-8 Input Voltage and Current Noise Density vs Frequency
XTR105 Input Bias and Offset Current vs Temperature
CSO: SHE
 
Figure 5-10 Input Bias and Offset Current vs Temperature
XTR105 Zero Output Current Error vs Temperature
 
Figure 5-12 Zero Output Current Error vs Temperature
XTR105 Input Offset Voltage Drift Production Distribution
CSO: TID
 
Figure 5-14 Input Offset Voltage Drift Production Distribution
XTR105 Current Source Drift Production Distribution
 
Figure 5-16 Current Source Drift Production Distribution
XTR105 VREG Output Voltage vs vREG Output Current
Above 1mA, zero output degrades
 
Figure 5-18 VREG Output Voltage vs vREG Output Current