SBOS069 Data sheet

SBOS069B October 1997 – December 2025 INA122

PRODUCTION DATA

5.6 Typical Characteristics

at T_A = +25°C and V_S = ±5V, all chips site origins (CSO), unless otherwise noted.

Figure 5-1 Gain vs Frequency

Figure 5-3 Positive Power Supply Rejection vs Frequency

Figure 5-5 Input Common-Mode Range vs Output Voltage, V_S = ±15V, G = 5

Figure 5-7 Voltage and Current Noise Density vs Frequency (RTI)

Figure 5-9 Total Harmonic Distortion+Noise vs Frequency

CSO: TID

Figure 5-11 Output Voltage Swing vs Output Current (Sourcing)

Figure 5-13 Small-Signal Step Response G = 5

CSO: SHE

Figure 5-15 Large-Signal Step Response G = 5

Figure 5-17 Input-Referred Noise Voltage 0.1Hz to 10Hz

Figure 5-2 Common-Mode Rejection vs Frequency

Figure 5-4 Negative Power Supply Rejection vs Frequency

Figure 5-6 Input Common-Mode Voltage vs Output Voltage, V_S = ±5V, G = 5

Figure 5-8 Quiescent Current vs Temperature

CSO: SHE

Figure 5-10 Output Voltage Swing vs Output Current

CSO: TID

Figure 5-12 Output Voltage Swing vs Output Current (Sinking)

Figure 5-14 Small-Signal Step Response G = 100

CSO: TID

Figure 5-16 Large-Signal Step Response G = 5