SBOS527G December   2010  – September 2025 TMP411-Q1 , TMP411D-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics (TMP411-Q1)
    6. 6.6  Electrical Characteristics (TMP411D-Q1)
    7. 6.7  Timing Characteristics
    8. 6.8  Timing Diagrams
    9. 6.9  Typical Characteristics (TMP411-Q1)
    10. 6.10 Typical Characteristics (TMP411D-Q1)
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Series Resistance Cancellation
      2. 7.3.2 Differential Input Capacitance
      3. 7.3.3 Temperature Measurement Data
      4. 7.3.4 THERM (PIN 4) and ALERT/ THERM2 (PIN 6)
      5. 7.3.5 Sensor Fault
      6. 7.3.6 Undervoltage Lockout (TMP411-Q1 Only)
      7. 7.3.7 Filtering
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode (SD)
      2. 7.4.2 One-Shot Conversion
    5. 7.5 Programming
      1. 7.5.1  Serial Interface
      2. 7.5.2  Bus Overview
      3. 7.5.3  Timing Diagrams
      4. 7.5.4  Serial Bus Address
      5. 7.5.5  Read/Write Operations
      6. 7.5.6  Time-Out Function
      7. 7.5.7  High-Speed Mode
      8. 7.5.8  General-Call Reset
      9. 7.5.9  Software Reset
      10. 7.5.10 SMBUS Alert Function
  9. 8 Register Map
    1. 8.1  Register Information
    2. 8.2  Pointer Register
    3. 8.3  Temperature Registers
    4. 8.4  Limit Registers
    5. 8.5  Status Register
    6. 8.6  Configuration Register
    7. 8.7  Resolution Register
    8. 8.8  Conversion Rate Register
    9. 8.9  N-factor Correction Register
    10. 8.10 Minimum and Maximum Registers
    11. 8.11 Consecutive Alert Register
    12. 8.12 THERM Hysteresis Register
    13. 8.13 Identification Registers
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

7.5.10 SMBUS Alert Function

The TMP411-Q1 and TMP411D-Q1 support the SMBus alert function. When pin 6 is configured as an alert output, the ALERT pin of the TMP411-Q1 and TMP411D-Q1 can be connected as an SMBus alert signal. When a controller detects an alert condition on the ALERT line, the controller sends an SMBus alert command (0001 1001) on the bus. If the ALERT pin of the TMP411-Q1 and TMP411D-Q1 devices is active, the device acknowledges the SMBus alert command and returns the target address on the SDA line. The eighth bit (LSB) of the target address byte indicates whether the temperature exceeding one of the temperature high limit settings or falling below one of the temperature low limit settings caused the alert condition. The bit is high if the temperature is greater than one of the temperature high limit settings; the bit is low if the temperature is less than or equal to one of the temperature low limit settings. See Figure 7-9 for details of this sequence.

If multiple devices on the bus respond to the SMBus alert command, arbitration during the target address portion of the SMBus alert command determines which device clears the alert status. If the TMP411-Q1 and TMP411D-Q1 win the arbitration, the ALERT pin becomes inactive at the completion of the SMBus alert command. If the TMP411-Q1 and TMP411D-Q1 devices lose the arbitration, the ALERT pin remains active.