SBOS998E June   2021  – March 2026 BUF802

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics Wide Bandwidth Mode
    6. 5.6 Electrical Characteristics Low Quiescent Current Mode
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input and Output Overvoltage Clamp
      2. 7.3.2 Adjustable Quiescent Current
      3. 7.3.3 ESD Structure
    4. 7.4 Device Functional Modes
      1. 7.4.1 Buffer Mode (BF Mode)
        1. 7.4.1.1 BUF802 Used in BF Mode for Clock Buffer
      2. 7.4.2 Composite Loop Mode (CL Mode)
        1. 7.4.2.1 Alternative Approach for Realizing Composite Loop
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Oscilloscope Front-End Amplifier Design
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Transforming a Wide-Bandwidth, 50Ω Input Signal Chain to High-Input Impedance
        1. 8.2.2.1 Detailed Design Procedure
        2. 8.2.2.2 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

8.2.1.2 Detailed Design Procedure

  • Input Impedance: The JFET-input stage of the BUF802 offers giga-ohms of input impedance, and therefore, enables the front-end to terminate with a 1MΩ resistor without affecting performance. A 50Ω resistance can also be switched in offering matched termination for high-frequency signals. The BUF802 enables the designer to use both 1MΩ and 50Ω termination in the same signal chain.
  • Noise: The total noise of the front-end amplifier is the function of the voltage and current noise of the BUF802, OPA140, and the resistors thermal noise. The dominant noise source, however, is contributed by the voltage noise of the BUF802 as a result of the noise presence across the complete bandwidth. Thus, the total RMS noise of the front-end amplifier is approximately equal to the voltage noise of BUF802 over 1GHz.

    The specified input-referred voltage noise of the BUF802 (see Section 5.5) is 2.3nV/√Hz. The total input referred RMS noise in a bandwidth of 1GHz is given by the following equation:

    Equation 1. E n R M S = 2.3 n V / √ H z × 1 G H z × 1.22 = 80 μ V R M S

    1.22 = Brick-wall correction factor. See TI Precision Labs – Op Amps: Noise – Spectral Density for detailed calculations.

    Figure 8-3 shows the total input-referred spot noise as a function of frequency. Assuming the oscilloscope has eight divisions on the screen and a highest resolution of 1mV, the full-scale reading is 8mVPP or 2.82mVRMS. Thus, the SNR of the front-end amplifier stage at the highest-resolution setting is:

    Equation 2. 20 × log ⁡ 2.82 m V R M S 80 µ V R M S = 31 d B
  • S11 Optimization: The front-end amplifier circuit requires an exact 50Ω termination to achieve the required S11 parameter of –15dB across the frequency. Although mounting an exact 50Ω resistance at the input of the front-end composite loop circuit is possible, the parasitic capacitance of the BUF802 appears in parallel to this 50Ω resistance, resulting in a net-imperfect termination.

    The parasitic input capacitance of BUF802 (IN pin) is 2.4pF. At 1GHz, this parasitic capacitance reduces to an impedance of 66.3Ω. Thus, the net input impedance seen by the signal at the input is:

    Equation 3. 66.3 Ω ∥ 50 Ω = 28.5 Ω

    This result is an imperfect termination for the 50Ω source, resulting in a poor S11. The addition of a 30Ω resistance in series with the input trace, and a 6.8nH inductor in series with the on-board 50Ω termination help isolate the input parasitic capacitance. This configuration also helps maintain the net input impedance at 50Ω. Figure 8-4 shows the S11 response of this modified circuit.

    BUF802 Net Input Impedance Figure 8-2 Net Input Impedance
  • Uniform Gain Across Frequency: The front-end amplifier circuit is designed with BUF802 and OPA140 connected in a composite loop. The loop splits the input signal into low- and high-frequency components, taking both components to the output through two different circuits (transfer functions) and recombining them to reproduce a net output signal. The end goal is to achieve a smooth transition between the two circuits and maintain a flat frequency response from AC until the frequency of interest.

    CL Mode of the BUF802 simplifies this design for achieving a flat frequency response from DC until the frequency of interest (1GHz in this case). To achieve a flat response, meet the following two conditions:

    1. High-frequency response pole fHF << low frequency pole fLF
    2. α/β = G

    where

    • α is the input attenuation factor
    • β is the inverse of the non-inverting gain of the precision amplifier
    • G is the dc gain of the main path of the BUF802

    G varies from device-to-device; therefore, trim either α or β to achieve a flat frequency response. In Figure 8-1, trim β using the RPOT.

    G is the typical value, (G = 0.971V/V) from Section 5.5 and

    Equation 4. α = 1 5 × 200 k Ω 200 k Ω + 800 k Ω

    Therefore, trim RPOT so that β ≅ 1/5.

    For the β network, use resistors that are an order of magnitude of resistance lower than the resistors used in the α network. Therefore, β resistor values of 80 kΩ and ≅ 20kΩ are chosen.

    fHF is the pole resulting from the 330pF series capacitor and the 10MΩ resistor on the In_Bias pin. Reduction in value of 10MΩ helps with the reduction of overdrive recovery time of the composite loop, but increases the fHF pole frequency.

    Equation 5. f H F = 1 2 × π × R × C = 1 2 × 3.14 × 10 M Ω × 330 p F = 48 H z

    fLF is the pole resulting from the gain bandwidth of the precision amplifier (OPA140), the auxiliary path bandwidth and other parasitic capacitance of the resistor network.

    Equation 6. f L F 1   o f   p r e c i s i o n   a m p l i f i e r = G B W × G A U X × β = 440 k H z

    where

    • GBW is the gain bandwidth product of the precision amplifier (OPA140) = 11MHz
    • GAUX is the gain from In_Aux to OUT = 0.2 V/V
    • 1/β is the external non-inverting gain set for the precision amplifier = 5 V/V

    The common mode input capacitor of the precision amplifier (CINPA) forms a pole with the Rα2 resulting in pole frequency of:

    Equation 7. f L F 2   o f   R α 2   a n d   C I N P A   o f   a m p l i f i e r = 1 2 × π × R a 2 × C I N P A = 28.4 k H z

    Since fLF2 < fLF1, fLF2 is considered as the dominant pole for the auxiliary path bandwidth. Based on the above value of fHF and fLF2, the required condition of fHF << fLF2 is met.

    CF, connected across the precision amplifier, is required to compensate for the parasitic capacitance and to make the overall poles and zeros cancel each other. Use the following equation to find the value of CF:

    Equation 8. C F = C I N P A × G × R α 2 R β 2 - 1

    where

    • CINPA is the common-mode input capacitance of the precision amplifier, the OPA140 in this case
    • G is the typical value, (G = 0.971V/V) from Section 5.5

    Plugging in the value of these components arrives approximately to CF = 61pF, rounding off to nearest standard capacitor CF = 56pF. In the final system, based on the quality of the flat-band response needed, CF is able to be trimmed along with RPOT in the final production flow.