SBOS998E June   2021  – March 2026 BUF802

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics Wide Bandwidth Mode
    6. 5.6 Electrical Characteristics Low Quiescent Current Mode
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input and Output Overvoltage Clamp
      2. 7.3.2 Adjustable Quiescent Current
      3. 7.3.3 ESD Structure
    4. 7.4 Device Functional Modes
      1. 7.4.1 Buffer Mode (BF Mode)
        1. 7.4.1.1 BUF802 Used in BF Mode for Clock Buffer
      2. 7.4.2 Composite Loop Mode (CL Mode)
        1. 7.4.2.1 Alternative Approach for Realizing Composite Loop
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Oscilloscope Front-End Amplifier Design
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Transforming a Wide-Bandwidth, 50Ω Input Signal Chain to High-Input Impedance
        1. 8.2.2.1 Detailed Design Procedure
        2. 8.2.2.2 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

5.7 Typical Characteristics

at TA = 25°C, VS = ±6V, RL = 100Ω || 400fF, RS = 25 Ω, VOCM = 0V (mid-supply), CLH and CLL tied to VS+ and VS–, respectively, R_Bias = 17.8kΩ, and wide bandwidth mode (unless otherwise noted)

BUF802 Frequency Response vs Output Voltage
Wide Bandwidth mode
Figure 5-1 Frequency Response vs Output Voltage
BUF802 Frequency Response vs Output Voltage,0.1dB Flatness
Wide Bandwidth mode
Figure 5-3 Frequency Response vs Output Voltage,
0.1dB Flatness
BUF802 Frequency Response vs Output Load
 
Figure 5-5 Frequency Response vs Output Load
BUF802 Frequency Response vs Capacitive Load
 
Figure 5-7 Frequency Response vs Capacitive Load
BUF802 Large-Signal Transient Response
Rising edge, VOUT = 1.2 VPP
Figure 5-9 Large-Signal Transient Response
BUF802 Small-Signal Transient Response
Rising edge, VOUT = 250 m VPP
Figure 5-11 Small-Signal Transient Response
BUF802 Harmonic Distortion vs Frequency
VOUT = 1 VPP
Figure 5-13 Harmonic Distortion vs Frequency
BUF802 Harmonic Distortion vs Supply Voltage
f = 500MHz
Figure 5-15 Harmonic Distortion vs Supply Voltage
BUF802 Harmonic Distortion vs Output Voltage
f = 1GHz
Figure 5-17 Harmonic Distortion vs Output Voltage
BUF802 Voltage Noise Density vs Frequency
 
Figure 5-19 Voltage Noise Density vs Frequency
BUF802 Auxiliary Path Frequency Response
With RC pole of 2kΩ and 10pF at IN_Aux pin
Figure 5-21 Auxiliary Path Frequency Response
BUF802 Output Impedance vs Frequency
 
Figure 5-23 Output Impedance vs Frequency
BUF802 Input Bias Current vs Temperature
40 units
Figure 5-25 Input Bias Current vs Temperature
BUF802 Quiescent Current vs Temperature
Wide bandwidth mode and low IQ mode
Figure 5-27 Quiescent Current vs Temperature
BUF802 DC Gain vs Temperature
Normalized to 25°C values, 40 units
Figure 5-29 DC Gain vs Temperature
BUF802 Offset Voltage vs Temperature
Normalized to 25°C values, 40 units
Figure 5-31 Offset Voltage vs Temperature
BUF802 Clamp Voltage Error Histogram
 
Figure 5-33 Clamp Voltage Error Histogram
BUF802 Frequency Response vs Output Voltage
Low Quiescent Current mode
Figure 5-2 Frequency Response vs Output Voltage
BUF802 Frequency Response vs Supply Voltage
 
Figure 5-4 Frequency Response vs Supply Voltage
BUF802 Frequency Response vs R_Bias Resistance
 
Figure 5-6 Frequency Response vs R_Bias Resistance
BUF802 Frequency Response vs Capacitive Load With Recommended RISO
 
Figure 5-8 Frequency Response vs Capacitive Load With Recommended RISO
BUF802 Large-Signal Transient Response
Falling edge, VOUT = 1.2 VPP
Figure 5-10 Large-Signal Transient Response
BUF802 Small-Signal Transient Response
Falling edge, VOUT = 250 m VPP
Figure 5-12 Small-Signal Transient Response
BUF802 Harmonic Distortion vs Frequency
VOUT = 2 VPP
Figure 5-14 Harmonic Distortion vs Frequency
BUF802 Harmonic Distortion vs Output Common-Mode Voltage
 
Figure 5-16 Harmonic Distortion vs Output Common-Mode Voltage
BUF802 Harmonic Distortion vs Output Load
f = 1GHz
Figure 5-18 Harmonic Distortion vs Output Load
BUF802 Current Noise Density vs Frequency
 
Figure 5-20 Current Noise Density vs Frequency
BUF802 Input Impedance vs Frequency
 
Figure 5-22 Input Impedance vs Frequency
BUF802 Input Bias Current Distribution
μ = 3.1 pA, σ = 1.03 pA
Figure 5-24 Input Bias Current Distribution
BUF802 Input Bias Current vs Input Common-Mode Voltage
 
Figure 5-26 Input Bias Current vs Input Common-Mode Voltage
BUF802 DC Gain Histogram
μ = 0.971V/V, σ = 0.000485V/V
Figure 5-28 DC Gain Histogram
BUF802 Offset Voltage Histogram
μ = 587.668mV, σ = 8.80778mV
Figure 5-30 Offset Voltage Histogram
BUF802 Transient Clamp Response
 
Figure 5-32 Transient Clamp Response
BUF802 Phase Noise
 
Figure 5-34 Phase Noise