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High-speed op amps (GBW ≥ 50 MHz)

BUF802

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Wide-bandwidth, 2.3-nV/√Hz, high-input impedance JFET buffer

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Data sheet

BUF802

ACTIVE
Data sheet Order now

Product details

Architecture FET / CMOS Input, Open Loop/Buffer Number of channels 1 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 9 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 13 GBW (typ) (MHz) 3100 BW at Acl (MHz) 3100 Acl, min spec gain (V/V) 1 Slew rate (typ) (V/µs) 7000 Vn at flatband (typ) (nV√Hz) 2.3 Vn at 1 kHz (typ) (nV√Hz) 10 Iq per channel (typ) (mA) 34 Vos (offset voltage at 25°C) (max) (mV) 800 Rail-to-rail No Features Adjustable BW/IQ/IOUT, Integrated Clamps Rating Catalog Operating temperature range (°C) -40 to 85 Input bias current (max) (pA) 25 Offset drift (typ) (µV/°C) 700 Iout (typ) (mA) 15 2nd harmonic (dBc) -55 3rd harmonic (dBc) -59 Frequency of harmonic distortion measurement (MHz) 1000
Architecture FET / CMOS Input, Open Loop/Buffer Number of channels 1 Total supply voltage (+5 V = 5, ±5 V = 10) (min) (V) 9 Total supply voltage (+5 V = 5, ±5 V = 10) (max) (V) 13 GBW (typ) (MHz) 3100 BW at Acl (MHz) 3100 Acl, min spec gain (V/V) 1 Slew rate (typ) (V/µs) 7000 Vn at flatband (typ) (nV√Hz) 2.3 Vn at 1 kHz (typ) (nV√Hz) 10 Iq per channel (typ) (mA) 34 Vos (offset voltage at 25°C) (max) (mV) 800 Rail-to-rail No Features Adjustable BW/IQ/IOUT, Integrated Clamps Rating Catalog Operating temperature range (°C) -40 to 85 Input bias current (max) (pA) 25 Offset drift (typ) (µV/°C) 700 Iout (typ) (mA) 15 2nd harmonic (dBc) -55 3rd harmonic (dBc) -59 Frequency of harmonic distortion measurement (MHz) 1000
VQFN (RGT) 16 9 mm² (3 mm × 3 mm)
  • Large-signal bandwidth (1VPP): 3.1GHz
  • Slew rate: 7000V/µs
  • Input voltage noise: 2.3nV/√Hz
  • 1% settling time: 0.7ns
  • Input-impedance: 50GΩ || 2.4pF
  • Capable of driving 50Ω load
  • Adjustable quiescent current for power and performance trade-off
  • Integrated input and output clamp with fast overdrive recovery
  • Voltage supply: ±4.5V to ±6.5V
  • Low phase noise
  • Large-signal bandwidth (1VPP): 3.1GHz
  • Slew rate: 7000V/µs
  • Input voltage noise: 2.3nV/√Hz
  • 1% settling time: 0.7ns
  • Input-impedance: 50GΩ || 2.4pF
  • Capable of driving 50Ω load
  • Adjustable quiescent current for power and performance trade-off
  • Integrated input and output clamp with fast overdrive recovery
  • Voltage supply: ±4.5V to ±6.5V
  • Low phase noise

The BUF802 device is an open-loop, unity gain buffer with a JFET input stage that offers low-noise, high-impedance buffering for data acquisition system (DAQ) front ends. The BUF802 supports DC-to-3.1GHz of bandwidth, while offering excellent distortion and noise performance across the frequency range.

The BUF802 can be used in a composite loop with a precision amplifier in applications where higher precision performance is required. The BUF802 uses a remarkable architecture to simplify the design of high-precision, wide-bandwidth composite loops.

The BUF802 features an adjustable quiescent current pin that enables designers to trade bandwidth and distortion for a lower quiescent current. This feature makes the device an excellent choice across a wide-frequency range. The BUF802 has integrated input and output clamps to protect the device and the subsequent signal-chain from overdrive voltages.

The BUF802 device is an open-loop, unity gain buffer with a JFET input stage that offers low-noise, high-impedance buffering for data acquisition system (DAQ) front ends. The BUF802 supports DC-to-3.1GHz of bandwidth, while offering excellent distortion and noise performance across the frequency range.

The BUF802 can be used in a composite loop with a precision amplifier in applications where higher precision performance is required. The BUF802 uses a remarkable architecture to simplify the design of high-precision, wide-bandwidth composite loops.

The BUF802 features an adjustable quiescent current pin that enables designers to trade bandwidth and distortion for a lower quiescent current. This feature makes the device an excellent choice across a wide-frequency range. The BUF802 has integrated input and output clamps to protect the device and the subsequent signal-chain from overdrive voltages.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet BUF802 Wide-Bandwidth, 2.3nV/√Hz, High-Input Impedance Buffer datasheet (Rev. E) PDF | HTML Mar 10, 2026
Design guide High-Impedance, 500MHz Bandwidth Oscilloscope Analog Front End Reference Design PDF | HTML Jul 29, 2026
Product overview Pairing High-Speed JFET Amplifiers With Hi-Z DAQ Systems PDF | HTML Apr 8, 2024
Application note Choosing an Amplifier for Wide Bandwidth, High-Impedance, Data Acquisition AFEs PDF | HTML Mar 2, 2023
Application brief How to Tune the S-Parameters of Your Analog Front-End Signal Chain PDF | HTML Feb 25, 2022
Technical article Achieving high-DC precision and wide large signal bandwidth with Hi-Z buffers PDF | HTML Jan 18, 2022

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

BUF802RGTEVM — BUF802 evaluation module high-speed, wide-bandwidth, 2.3-nV/√Hz, input buffer in RGT package

The BUF802RGTEVM is designed to easily demonstrate the functionality and versatility of the buffer. The EVM features two separate circuit configurations: a composite loop with a precision amplifier and a standalone BUF802 circuit. It can be used with split or single supplies, and includes SMA (...)
User guide: PDF | HTML
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Simulation model

BUF802 PSpice model

SBOMC43.ZIP (187 KB) - PSpice model
Supported products & hardware
Simulation model

BUF802 TINA-TI Reference Circuit (Rev. D)

SBOMBQ8D (5895 KB) - TINA-TI Spice model
Supported products & hardware
Reference design

TIDA-01022 — Flexible 3.2-GSPS multi-channel AFE reference design for DSOs, radar and 5G wireless test systems

This high speed multi-channel data capture reference design enables optimum system performance. System designers needs to consider critical design parameters like clock jitter and skew for high speed multi-channel clock generation, which affects overall system SNR, SFDR, channel to channel skew (...)
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VQFN (RGT) 16 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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