SBOSA78 March   2026 INA1H182-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Setting the Gain
        1. 6.3.1.1 Gain Drift
      2. 6.3.2 EMI Rejection
      3. 6.3.3 Input Common-Mode Range
      4. 6.3.4 Input Protection
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Reference Pin
      2. 7.1.2 Input Bias Current Return Path
    2. 7.2 Typical Applications
      1. 7.2.1 Resistor Temperature Detector Signal Conditioning Circuit
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Procedure
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

6.1 Overview

The INA1H182-SEP is a monolithic precision instrumentation amplifier that incorporates a current-feedback input stage and a four-resistor difference amplifier output stage. The functional block diagram in the next section shows how the differential input voltage is buffered by Q1 and Q2 and is forced across RG, which causes a signal current to flow through RG, R1, and R2. The output difference amplifier, A3, removes the common-mode component of the input signal and refers the output signal to the REF pin. The VBE and voltage drop across R1 and R2 produces output voltages on A1 and A2 that are approximately 0.8V lower than the input voltages.

Each input is protected by two field-effect transistors (FETs) that provide a low series resistance under normal signal conditions, and preserve excellent noise performance. When excessive voltage is applied, these transistors limit input current to approximately 8mA.